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FMC ADC 100M 14b 4cha - Software
Commit 7aa6b8b2 authored by Federico Vaga's avatar Federico Vaga
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attribute: index ext attr with enum 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent eb0d1d7e
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Showing with 62 additions and 14 deletions
kernel/fa-irq.c
View file @ 7aa6b8b2
......@@ -84,9 +84,9 @@ void zfad_dma_done(struct zio_cset *cset)
ctrl->tstamp.bins = *(++trig_timetag);
/* Acquisition start Timetag */
ctrl->attr_channel.ext_val[13] = ztstamp.secs;
ctrl->attr_channel.ext_val[14] = ztstamp.ticks;
ctrl->attr_channel.ext_val[15] = ztstamp.bins;
ctrl->attr_channel.ext_val[ZFAD_ATTR_ACQ_START_S] = ztstamp.secs;
ctrl->attr_channel.ext_val[ZFAD_ATTR_ACQ_START_C] = ztstamp.ticks;
ctrl->attr_channel.ext_val[ZFAD_ATTR_ACQ_START_F] = ztstamp.bins;
/* resize the datalen and clear stamp from data block */
block->datalen -= FA_TRIG_TIMETAG_BYTES;
......
kernel/fa-zio-trg.c
View file @ 7aa6b8b2
......@@ -44,35 +44,35 @@ static struct zio_attribute zfat_ext_zattr[] = {
* 0: internal (data threshold)
* 1: external (front panel trigger input)
*/
ZIO_ATTR_EXT("external", ZIO_RW_PERM, ZFAT_CFG_HW_SEL, 0),
[ZFAT_ATTR_EXT] = ZIO_ATTR_EXT("external", ZIO_RW_PERM, ZFAT_CFG_HW_SEL, 0),
/*
* Internal Hardware trigger polarity
* 0: positive edge/slope
* 1: negative edge/slope
*/
ZIO_ATTR_EXT("polarity", ZIO_RW_PERM, ZFAT_CFG_HW_POL, 0),
[ZFAT_ATTR_POL] = ZIO_ATTR_EXT("polarity", ZIO_RW_PERM, ZFAT_CFG_HW_POL, 0),
/*
* Channel selection for internal trigger
* 0: channel 1, 1: channel 2, 2: channel 3, 3: channel 4
*/
ZIO_ATTR_EXT("int-channel", ZIO_RW_PERM, ZFAT_CFG_INT_SEL, 0),
[ZFAT_ATTR_INT_CHAN] = ZIO_ATTR_EXT("int-channel", ZIO_RW_PERM, ZFAT_CFG_INT_SEL, 0),
/* Internal trigger threshold value is 2 complement format */
ZIO_ATTR_EXT("int-threshold", ZIO_RW_PERM, ZFAT_CFG_THRES, 0),
[ZFAT_ATTR_INT_THRES] = ZIO_ATTR_EXT("int-threshold", ZIO_RW_PERM, ZFAT_CFG_THRES, 0),
/*
* Delay to apply on the trigger in sampling clock period. The default
* clock frequency is 100MHz (period = 10ns)
*/
ZIO_ATTR_EXT("delay", ZIO_RW_PERM, ZFAT_DLY, 0),
[ZFAT_ATTR_DELAY] = ZIO_ATTR_EXT("delay", ZIO_RW_PERM, ZFAT_DLY, 0),
/* Software Trigger */
/* Enable (1) or disable (0) software trigger */
ZIO_PARAM_EXT("sw-trg-enable", ZIO_RW_PERM, ZFAT_CFG_SW_EN, 0),
ZIO_PARAM_EXT("sw-trg-fire", ZIO_WO_PERM, ZFAT_SW, 0),
[ZFAT_ATTR_SW_EN] = ZIO_PARAM_EXT("sw-trg-enable", ZIO_RW_PERM, ZFAT_CFG_SW_EN, 0),
[ZFAT_ATTR_SW_FIRE] = ZIO_PARAM_EXT("sw-trg-fire", ZIO_WO_PERM, ZFAT_SW, 0),
/* last trigger time stamp */
ZIO_PARAM_EXT("tstamp-trg-lst-s", ZIO_RO_PERM, ZFA_UTC_TRIG_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-t", ZIO_RO_PERM, ZFA_UTC_TRIG_COARSE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-b", ZIO_RO_PERM, ZFA_UTC_TRIG_FINE, 0),
[ZFAT_ATTR_TRG_S] = ZIO_PARAM_EXT("tstamp-trg-lst-s", ZIO_RO_PERM, ZFA_UTC_TRIG_SECONDS, 0),
[ZFAT_ATTR_TRG_C] = ZIO_PARAM_EXT("tstamp-trg-lst-t", ZIO_RO_PERM, ZFA_UTC_TRIG_COARSE, 0),
[ZFAT_ATTR_TRG_F] = ZIO_PARAM_EXT("tstamp-trg-lst-b", ZIO_RO_PERM, ZFA_UTC_TRIG_FINE, 0),
};
......@@ -114,7 +114,7 @@ static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
break;
case ZFAT_SW:
/* Fire if software trigger is enabled (index 5) */
if (!ti->zattr_set.ext_zattr[5].value) {
if (!ti->zattr_set.ext_zattr[ZFAT_ATTR_SW_EN].value) {
dev_info(dev, "sw trigger is not enabled\n");
return -EPERM;
}
......
kernel/fmc-adc.h
View file @ 7aa6b8b2
......@@ -219,6 +219,54 @@ enum zfadc_dregs_enum {
ZFA_HW_PARAM_COMMON_LAST,
};
/*
* Trigger Extended Attribute Enumeration
*/
enum fa_trig_ext_attributes {
/*
* The trigger extended attribute order is the same in the declaration
* and in the zio_control, so we can always use enumeration. But, the
* enumeration must start with 0 followed by only consecutive value.
*/
ZFAT_ATTR_EXT = 0,
ZFAT_ATTR_POL,
ZFAT_ATTR_INT_CHAN,
ZFAT_ATTR_INT_THRES,
ZFAT_ATTR_DELAY,
ZFAT_ATTR_SW_EN,
ZFAT_ATTR_SW_FIRE,
ZFAT_ATTR_TRG_S,
ZFAT_ATTR_TRG_C,
ZFAT_ATTR_TRG_F,
};
/*
* Device Extended Attribute Enumeration
*/
enum fa_dev_ext_attributes {
/*
* NOTE: At the moment the only extended attributes we have in
* the device hierarchy are in the cset level, so we can safely
* start from index 0
*/
ZFAD_ATTR_DECI = 0,
ZFAD_ATTR_CH0_OFFSET,
ZFAD_ATTR_CH1_OFFSET,
ZFAD_ATTR_CH2_OFFSET,
ZFAD_ATTR_CH3_OFFSET,
ZFAD_ATTR_CH0_VREF,
ZFAD_ATTR_CH1_VREF,
ZFAD_ATTR_CH2_VREF,
ZFAD_ATTR_CH3_VREF,
ZFAD_ATTR_CH0_50TERM,
ZFAD_ATTR_CH1_50TERM,
ZFAD_ATTR_CH2_50TERM,
ZFAD_ATTR_CH3_50TERM,
ZFAD_ATTR_ACQ_START_S,
ZFAD_ATTR_ACQ_START_C,
ZFAD_ATTR_ACQ_START_F,
};
/*
* ADC parameter id not mapped to Hw register
* Id is used as zio attribute id
......
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