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FMC ADC 100M 14b 4cha - Software
Commit da6dd2c0 authored by Federico Vaga's avatar Federico Vaga
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Update to zio-beta4 version 

Signed-off-by: 's avatarFederico Vaga <federico.vaga@gmail.com>
parent e28c93fe
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Showing with 85 additions and 90 deletions
fa-dma.c
View file @ da6dd2c0
......@@ -94,8 +94,11 @@ int zfad_map_dma(struct zio_cset *cset)
int err;
pages = zfat_calculate_nents(block);
if (!pages)
if (!pages) {
dev_err(&cset->head.dev, "No pages to transfer (datalen=%li)\n",
block->datalen);
return -EINVAL;
}
dev_dbg(&cset->head.dev, "using %d pages for transfer\n", pages);
/* Create sglists for the transfers */
......
fa-zio-drv.c
View file @ da6dd2c0
......@@ -130,8 +130,8 @@ const struct zio_field_desc zfad_regs[] = {
};
/* zio device attributes */
static DEFINE_ZATTR_STD(ZDEV, zfad_cset_std_zattr) = {
ZATTR_REG(zdev, ZATTR_NBITS, S_IRUGO, ZFA_SW_R_NOADDRES_NBIT, 14),
static ZIO_ATTR_DEFINE_STD(ZIO_DEV, zfad_cset_std_zattr) = {
ZIO_ATTR(zdev, ZIO_ATTR_NBITS, S_IRUGO, ZFA_SW_R_NOADDRES_NBIT, 14),
};
static struct zio_attribute zfad_cset_ext_zattr[] = {
/*
......@@ -140,20 +140,20 @@ static struct zio_attribute zfad_cset_ext_zattr[] = {
* acquisition you can decimate samples. 0 is a forbidden value, 1
* for the maximum speed.
*/
ZATTR_EXT_REG("sample-decimation", S_IRUGO | S_IWUGO, ZFAT_SR_DECI, 1),
ZIO_ATTR_EXT("sample-decimation", S_IRUGO | S_IWUGO, ZFAT_SR_DECI, 1),
/*
* State machine commands
* 1: start
* 2: stop
*/
PARAM_EXT_REG("fsm-command", S_IWUGO, ZFA_CTL_FMS_CMD, 0),
ZIO_PARAM_EXT("fsm-command", S_IWUGO, ZFA_CTL_FMS_CMD, 0),
/*
* Automatic start acquisition
* 1: enabled
* 0: disabled
*/
PARAM_EXT_REG("fsm-auto-start", S_IRUGO | S_IWUGO, ZFA_SW_R_NOADDERS_AUTO, 0),
ZIO_PARAM_EXT("fsm-auto-start", S_IRUGO | S_IWUGO, ZFA_SW_R_NOADDERS_AUTO, 0),
/*
* fsm - status of the state machine:
* 1: IDLE
......@@ -163,37 +163,37 @@ static struct zio_attribute zfad_cset_ext_zattr[] = {
* 5: DECR_SHOT
* 7: Illegal
* */
PARAM_EXT_REG("fsm-state", S_IRUGO, ZFA_STA_FSM, 0),
ZIO_PARAM_EXT("fsm-state", S_IRUGO, ZFA_STA_FSM, 0),
/* last acquisition start time stamp */
PARAM_EXT_REG("tstamp-acq-str-s", S_IRUGO, ZFA_UTC_ACQ_START_SECONDS, 0),
PARAM_EXT_REG("tstamp-acq-str-t", S_IRUGO, ZFA_UTC_ACQ_START_COARSE, 0),
PARAM_EXT_REG("tstamp-acq-str-b", S_IRUGO, ZFA_UTC_ACQ_START_FINE, 0),
ZIO_PARAM_EXT("tstamp-acq-str-s", S_IRUGO, ZFA_UTC_ACQ_START_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-acq-str-t", S_IRUGO, ZFA_UTC_ACQ_START_COARSE, 0),
ZIO_PARAM_EXT("tstamp-acq-str-b", S_IRUGO, ZFA_UTC_ACQ_START_FINE, 0),
/* last acquisition end time stamp */
PARAM_EXT_REG("tstamp-acq-end-s", S_IRUGO, ZFA_UTC_ACQ_END_SECONDS, 0),
PARAM_EXT_REG("tstamp-acq-end-t", S_IRUGO, ZFA_UTC_ACQ_END_COARSE, 0),
PARAM_EXT_REG("tstamp-acq-end-b", S_IRUGO, ZFA_UTC_ACQ_END_FINE, 0),
ZIO_PARAM_EXT("tstamp-acq-end-s", S_IRUGO, ZFA_UTC_ACQ_END_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-acq-end-t", S_IRUGO, ZFA_UTC_ACQ_END_COARSE, 0),
ZIO_PARAM_EXT("tstamp-acq-end-b", S_IRUGO, ZFA_UTC_ACQ_END_FINE, 0),
/* last acquisition stop time stamp */
PARAM_EXT_REG("tstamp-acq-stp-s", S_IRUGO, ZFA_UTC_ACQ_STOP_SECONDS, 0),
PARAM_EXT_REG("tstamp-acq-stp-t", S_IRUGO, ZFA_UTC_ACQ_STOP_COARSE, 0),
PARAM_EXT_REG("tstamp-acq-stp-b", S_IRUGO, ZFA_UTC_ACQ_STOP_FINE, 0),
ZIO_PARAM_EXT("tstamp-acq-stp-s", S_IRUGO, ZFA_UTC_ACQ_STOP_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-acq-stp-t", S_IRUGO, ZFA_UTC_ACQ_STOP_COARSE, 0),
ZIO_PARAM_EXT("tstamp-acq-stp-b", S_IRUGO, ZFA_UTC_ACQ_STOP_FINE, 0),
/* Reset all channel offset */
PARAM_EXT_REG("rst-ch-offset", S_IWUGO, ZFA_CTL_DAC_CLR_N, 1),
ZIO_PARAM_EXT("rst-ch-offset", S_IWUGO, ZFA_CTL_DAC_CLR_N, 1),
ZATTR_EXT_REG("ch1-offset", S_IRUGO | S_IWUGO, ZFA_CH1_OFFSET, 0),
ZATTR_EXT_REG("ch2-offset", S_IRUGO | S_IWUGO, ZFA_CH2_OFFSET, 0),
ZATTR_EXT_REG("ch3-offset", S_IRUGO | S_IWUGO, ZFA_CH3_OFFSET, 0),
ZATTR_EXT_REG("ch4-offset", S_IRUGO | S_IWUGO, ZFA_CH4_OFFSET, 0),
ZIO_ATTR_EXT("ch1-offset", S_IRUGO | S_IWUGO, ZFA_CH1_OFFSET, 0),
ZIO_ATTR_EXT("ch2-offset", S_IRUGO | S_IWUGO, ZFA_CH2_OFFSET, 0),
ZIO_ATTR_EXT("ch3-offset", S_IRUGO | S_IWUGO, ZFA_CH3_OFFSET, 0),
ZIO_ATTR_EXT("ch4-offset", S_IRUGO | S_IWUGO, ZFA_CH4_OFFSET, 0),
ZATTR_EXT_REG("ch1-vref", S_IRUGO | S_IWUGO, ZFA_CH1_CTL_RANGE, 0),
ZATTR_EXT_REG("ch2-vref", S_IRUGO | S_IWUGO, ZFA_CH2_CTL_RANGE, 0),
ZATTR_EXT_REG("ch3-vref", S_IRUGO | S_IWUGO, ZFA_CH3_CTL_RANGE, 0),
ZATTR_EXT_REG("ch4-vref", S_IRUGO | S_IWUGO, ZFA_CH4_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch1-vref", S_IRUGO | S_IWUGO, ZFA_CH1_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch2-vref", S_IRUGO | S_IWUGO, ZFA_CH2_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch3-vref", S_IRUGO | S_IWUGO, ZFA_CH3_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch4-vref", S_IRUGO | S_IWUGO, ZFA_CH4_CTL_RANGE, 0),
};
/* FIXME Unused until TLV control will be available */
static DEFINE_ZATTR_STD(ZDEV, zfad_chan_std_zattr) = {
static ZIO_ATTR_DEFINE_STD(ZIO_DEV, zfad_chan_std_zattr) = {
/* the offset is complement 2 format */
ZATTR_REG(zdev, ZATTR_OFFSET, S_IRUGO | S_IWUGO, ZFA_CHx_OFFSET, 0),
ZIO_ATTR(zdev, ZIO_ATTR_OFFSET, S_IRUGO | S_IWUGO, ZFA_CHx_OFFSET, 0),
/*
* in-range
* 0x23 (35): 100mV range
......@@ -201,17 +201,17 @@ static DEFINE_ZATTR_STD(ZDEV, zfad_chan_std_zattr) = {
* 0x45 (69): 10V range
* 0x00 (0): Open input
*/
ZATTR_REG(zdev, ZATTR_VREFTYPE, S_IRUGO | S_IWUGO, ZFA_CHx_CTL_RANGE, 0x11),
ZIO_ATTR(zdev, ZIO_ATTR_VREFTYPE, S_IRUGO | S_IWUGO, ZFA_CHx_CTL_RANGE, 0x11),
};
static struct zio_attribute zfad_chan_ext_zattr[] = {
PARAM_EXT_REG("current-value", S_IRUGO, ZFA_CHx_STA, 0),
ZIO_PARAM_EXT("current-value", S_IRUGO, ZFA_CHx_STA, 0),
};
static struct zio_attribute zfad_dev_ext_zattr[] = {
/* Get Mezzanine temperature from onewire */
PARAM_EXT_REG("temperature", S_IRUGO, ZFA_SW_R_NOADDRES_TEMP, 0),
ZIO_PARAM_EXT("temperature", S_IRUGO, ZFA_SW_R_NOADDRES_TEMP, 0),
};
/* Calculate correct index for channel from CHx indexes */
static inline int zfad_get_chx_index(unsigned long addr,
......@@ -356,7 +356,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
int i, err;
i = 4; /* FIXME temporary, to get chan number */
switch (zattr->priv.addr) {
switch (zattr->id) {
case ZFA_SW_R_NOADDERS_AUTO:
enable_auto_start = usr_val;
return 0;
......@@ -387,7 +387,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
dev_err(dev, "max-sample-rate minimum value is 1\n");
return -EINVAL;
}
reg = &zfad_regs[zattr->priv.addr];
reg = &zfad_regs[zattr->id];
break;
/* FIXME temporary until TLV control */
case ZFA_CH1_CTL_RANGE:
......@@ -407,7 +407,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
if (err)
return err;
case ZFA_CHx_STA:
i = zfad_get_chx_index(zattr->priv.addr, to_zio_chan(dev));
i = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
reg = &zfad_regs[i];
break;
case ZFA_CTL_FMS_CMD:
......@@ -415,7 +415,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
if (err)
return err;
default:
reg = &zfad_regs[zattr->priv.addr];
reg = &zfad_regs[zattr->id];
}
return zfa_common_conf_set(fa, reg, usr_val);
......@@ -428,7 +428,7 @@ static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
struct fa_dev *fa = get_zfadc(dev);
int i;
switch (zattr->priv.addr) {
switch (zattr->id) {
/* FIXME temporary until TLV control */
case ZFA_CH1_OFFSET:
case ZFA_CH2_OFFSET:
......@@ -445,11 +445,11 @@ static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
return 0;
case ZFA_CHx_CTL_RANGE:
case ZFA_CHx_STA:
i = zfad_get_chx_index(zattr->priv.addr, to_zio_chan(dev));
i = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
reg = &zfad_regs[i];
break;
default:
reg = &zfad_regs[zattr->priv.addr];
reg = &zfad_regs[zattr->id];
}
zfa_common_info_get(fa, reg, usr_val);
......@@ -543,7 +543,7 @@ static int zfad_init_cset(struct zio_cset *cset)
/* Trigger registers */
/* Set to single shot mode by default */
zfa_common_conf_set(fa, &zfad_regs[ZFAT_SHOTS_NB], 1);
cset->ti->zattr_set.std_zattr[ZATTR_TRIG_REENABLE].value = 0;
cset->ti->zattr_set.std_zattr[ZIO_ATTR_TRIG_REENABLE].value = 0;
/* Disable Software trigger*/
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_SW_EN], 0);
/* Enable Hardware trigger*/
......@@ -571,9 +571,9 @@ static struct zio_cset zfad_cset[] = {
.ssize = 2,
.n_chan = 4,
.chan_template = &zfad_chan_tmpl,
.flags = ZCSET_TYPE_ANALOG | /* is analog */
.flags = ZIO_CSET_TYPE_ANALOG | /* is analog */
ZIO_DIR_INPUT | /* is input */
ZCSET_INTERLEAVE_ONLY,/* interleave only */
ZIO_CSET_INTERLEAVE_ONLY,/* interleave only */
.zattr_set = {
.std_zattr = zfad_cset_std_zattr,
.ext_zattr = zfad_cset_ext_zattr,
......@@ -584,7 +584,6 @@ static struct zio_cset zfad_cset[] = {
};
static struct zio_device zfad_tmpl = {
.owner = THIS_MODULE,
.config = zio_internal_zdev_config,
.s_op = &zfad_s_op,
.flags = 0,
.cset = zfad_cset,
......
fa-zio-trg.c
View file @ da6dd2c0
......@@ -39,11 +39,11 @@ struct zfat_block {
#define to_zfat_instance(_ti) container_of(_ti, struct zfat_instance, ti)
/* zio trigger attributes */
static DEFINE_ZATTR_STD(TRIG, zfat_std_zattr) = {
static ZIO_ATTR_DEFINE_STD(ZIO_TRG, zfat_std_zattr) = {
/* Number of shots */
ZATTR_REG(trig, ZATTR_TRIG_REENABLE, S_IRUGO | S_IWUGO, ZFAT_SHOTS_NB, 0),
ZATTR_REG(trig, ZATTR_TRIG_PRE_SAMP, S_IRUGO | S_IWUGO, ZFAT_PRE, 0),
ZATTR_REG(trig, ZATTR_TRIG_POST_SAMP, S_IRUGO | S_IWUGO, ZFAT_POST, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_REENABLE, S_IRUGO | S_IWUGO, ZFAT_SHOTS_NB, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_PRE_SAMP, S_IRUGO | S_IWUGO, ZFAT_PRE, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_POST_SAMP, S_IRUGO | S_IWUGO, ZFAT_POST, 0),
};
static struct zio_attribute zfat_ext_zattr[] = {
/* Config register */
......@@ -51,35 +51,35 @@ static struct zio_attribute zfat_ext_zattr[] = {
* 0: internal (data threshold)
* 1: external (front panel trigger input)
*/
ZATTR_EXT_REG("external", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_SEL, 0),
ZIO_ATTR_EXT("external", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_SEL, 0),
/*
* Internal Hardware trigger polarity
* 0: positive edge/slope
* 1: negative edge/slope
*/
ZATTR_EXT_REG("polarity", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_POL, 0),
ZIO_ATTR_EXT("polarity", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_POL, 0),
/*
* Channel selection for internal trigger
* 0: channel 1, 1: channel 2, 2: channel 3, 3: channel 4
*/
ZATTR_EXT_REG("int-channel", S_IRUGO | S_IWUGO, ZFAT_CFG_INT_SEL, 0),
ZIO_ATTR_EXT("int-channel", S_IRUGO | S_IWUGO, ZFAT_CFG_INT_SEL, 0),
/* Internal trigger threshold value is 2 complement format */
ZATTR_EXT_REG("int-threshold", S_IRUGO | S_IWUGO, ZFAT_CFG_THRES, 0),
ZIO_ATTR_EXT("int-threshold", S_IRUGO | S_IWUGO, ZFAT_CFG_THRES, 0),
/*
* Delay to apply on the trigger in sampling clock period. The default
* clock frequency is 100MHz (period = 10ns)
*/
ZATTR_EXT_REG("delay", S_IRUGO | S_IWUGO, ZFAT_DLY, 0),
ZIO_ATTR_EXT("delay", S_IRUGO | S_IWUGO, ZFAT_DLY, 0),
/* Software Trigger */
/* Enable (1) or disable (0) software trigger */
PARAM_EXT_REG("sw-trg-enable", S_IRUGO | S_IWUGO, ZFAT_CFG_SW_EN, 0),
PARAM_EXT_REG("sw-trg-fire", S_IWUGO, ZFAT_SW, 0),
ZIO_PARAM_EXT("sw-trg-enable", S_IRUGO | S_IWUGO, ZFAT_CFG_SW_EN, 0),
ZIO_PARAM_EXT("sw-trg-fire", S_IWUGO, ZFAT_SW, 0),
/* last trigger time stamp */
PARAM_EXT_REG("tstamp-trg-lst-s", S_IRUGO, ZFA_UTC_TRIG_SECONDS, 0),
PARAM_EXT_REG("tstamp-trg-lst-t", S_IRUGO, ZFA_UTC_TRIG_COARSE, 0),
PARAM_EXT_REG("tstamp-trg-lst-b", S_IRUGO, ZFA_UTC_TRIG_FINE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-s", S_IRUGO, ZFA_UTC_TRIG_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-t", S_IRUGO, ZFA_UTC_TRIG_COARSE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-b", S_IRUGO, ZFA_UTC_TRIG_FINE, 0),
};
static int zfat_overflow_detection(struct zio_ti *ti, unsigned int addr,
......@@ -91,9 +91,9 @@ static int zfat_overflow_detection(struct zio_ti *ti, unsigned int addr,
if (!addr)
return 0;
pre_t = addr == ZFAT_PRE ? val : ti_zattr[ZATTR_TRIG_PRE_SAMP].value;
post_t = addr == ZFAT_POST ? val : ti_zattr[ZATTR_TRIG_POST_SAMP].value;
nshot_t = addr == ZFAT_SHOTS_NB ? val : ti_zattr[ZATTR_TRIG_REENABLE].value + 1;
pre_t = addr == ZFAT_PRE ? val : ti_zattr[ZIO_ATTR_TRIG_PRE_SAMP].value;
post_t = addr == ZFAT_POST ? val : ti_zattr[ZIO_ATTR_TRIG_POST_SAMP].value;
nshot_t = addr == ZFAT_SHOTS_NB ? val : ti_zattr[ZIO_ATTR_TRIG_REENABLE].value + 1;
if (((pre_t + post_t) * ti->cset->ssize * nshot_t) >= FA_MAX_ACQ_BYTE) {
dev_err(&ti->head.dev, "cannot acquire, device memory overflow\n");
......@@ -105,13 +105,13 @@ static int zfat_overflow_detection(struct zio_ti *ti, unsigned int addr,
static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
uint32_t usr_val)
{
const struct zio_field_desc *reg = &zfad_regs[zattr->priv.addr];
const struct zio_field_desc *reg = &zfad_regs[zattr->id];
struct fa_dev *fa = get_zfadc(dev);
struct zio_ti *ti = to_zio_ti(dev);
uint32_t tmp_val = usr_val;
int err = 0;
switch (zattr->priv.addr) {
switch (zattr->id) {
case ZFAT_SHOTS_NB:
/*
* Increase the reenable by 1 to be choerent with the
......@@ -124,7 +124,7 @@ static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
++tmp_val;
case ZFAT_PRE:
case ZFAT_POST:
err = zfat_overflow_detection(ti, zattr->priv.addr, tmp_val);
err = zfat_overflow_detection(ti, zattr->id, tmp_val);
if (err)
return err;
break;
......@@ -135,7 +135,7 @@ static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
return -EPERM;
}
/* Fire if nsamples!=0 */
if (!ti->cset->interleave->current_ctrl->nsamples) {
if (!ti->nsamples) {
dev_err(dev, "there aren't samples to acquire");
return -EINVAL;
}
......@@ -155,8 +155,8 @@ static int zfat_info_get(struct device *dev, struct zio_attribute *zattr,
{
struct fa_dev *fa = get_zfadc(dev);
zfa_common_info_get(fa, &zfad_regs[zattr->priv.addr], usr_val);
if (zattr->priv.addr == ZFAT_SHOTS_NB)
zfa_common_info_get(fa, &zfad_regs[zattr->id], usr_val);
if (zattr->id == ZFAT_SHOTS_NB)
(*usr_val)--;
return 0;
}
......@@ -297,7 +297,6 @@ static void zfat_irq_trg_fire(struct zfat_instance *zfat)
struct zio_channel *interleave = ti->cset->interleave;
struct zio_buffer_type *zbuf = ti->cset->zbuf;
struct fa_dev *fa = ti->cset->zdev->priv_d;
struct zio_control *ctrl;
struct zio_block *block;
struct zfat_block *zfat_block;
unsigned long flags;
......@@ -310,7 +309,7 @@ static void zfat_irq_trg_fire(struct zfat_instance *zfat)
* n_chan - 1 because of interleaved channel
*/
size = interleave->current_ctrl->ssize *
interleave->current_ctrl->nsamples * (ti->cset->n_chan - 1);
ti->nsamples * (ti->cset->n_chan - 1);
/*
* Immediately update the pointer to the last block of data because if
* block allocation fail, we must ready for the next block. If we don't
......@@ -325,31 +324,25 @@ static void zfat_irq_trg_fire(struct zfat_instance *zfat)
return;
zfat_block->dev_addr = fa->lst_dev_mem - size; /* previous block */
/* Allocate and update control */
ctrl = zio_alloc_control(GFP_ATOMIC);
if (!ctrl)
goto out;
interleave->current_ctrl->seq_num++;
zfat_get_time_stamp(fa, &interleave->current_ctrl->tstamp);
memcpy(ctrl, interleave->current_ctrl, ZIO_CONTROL_SIZE);
/* Allocate a new block for DMA transfer */
block = zbuf->b_op->alloc_block(interleave->bi, ctrl, size,
GFP_ATOMIC);
block = zbuf->b_op->alloc_block(interleave->bi, size, GFP_ATOMIC);
if (IS_ERR(block)) {
dev_err(&ti->cset->head.dev, "can't alloc block\n");
goto out_block;
goto out;
}
zfat_block->block = block;
/* Update the current control: sequence, nsamples and tstamp */
interleave->current_ctrl->seq_num++;
interleave->current_ctrl->nsamples = ti->nsamples;
zfat_get_time_stamp(fa, &interleave->current_ctrl->tstamp);
/* Copy the updated control into the block */
memcpy(zio_get_ctrl(block), interleave->current_ctrl, ZIO_CONTROL_SIZE);
/* Add to the list of prepared blocks */
zfat_block->block = block;
spin_lock_irqsave(&zfat->lock, flags);
list_add_tail(&zfat_block->list, &zfat->list_block);
spin_unlock_irqrestore(&zfat->lock, flags);
return;
out_block:
zio_free_control(ctrl);
out:
kfree(zfat_block);
}
......@@ -506,6 +499,7 @@ static void zfat_data_done(struct zio_cset *cset)
if (!block)
return;
/* Store block in the ZIO buffer */
if (bi->b_op->store_block(bi, block)) { /* may fail, no prob */
bi->b_op->free_block(bi, block);
......@@ -548,10 +542,9 @@ static const struct zio_trigger_operations zfat_ops = {
.create = zfat_create,
.destroy = zfat_destroy,
.change_status = zfat_change_status,
.data_done = zfat_data_done,
.input_fire = zfat_start_next_dma,
.abort = zfat_abort,
.config = zio_internal_trig_config,
.__data_done = zfat_data_done,
.__input_fire = zfat_start_next_dma,
.__abort = zfat_abort,
};
/* Definition of the trigger type */
......
fmc-adc.h
View file @ da6dd2c0
......@@ -29,7 +29,7 @@ extern int enable_auto_start;
/* ADC Calibration */
#define FA_CAL_PTR 0x0100 /* 256 Byte */
#define FA_CAL_PTR 0x0400 /* 1 KByte */
#define FA_CAL_LEN 108
enum fa_input_range {
......@@ -267,13 +267,13 @@ enum zfat_irq {
static inline struct fa_dev *get_zfadc(struct device *dev)
{
switch (to_zio_head(dev)->zobj_type) {
case ZDEV:
case ZIO_DEV:
return to_zio_dev(dev)->priv_d;
case ZCSET:
case ZIO_CSET:
return to_zio_cset(dev)->zdev->priv_d;
case ZCHAN:
case ZIO_CHAN:
return to_zio_chan(dev)->cset->zdev->priv_d;
case ZTI:
case ZIO_TI:
return to_zio_ti(dev)->cset->zdev->priv_d;
default:
return NULL;
......
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