Commit e3700a3a authored by Federico Vaga's avatar Federico Vaga

kernel: gateware v5 updates

The gateware version 5 does not have anymore the selection
between internal or external trigger. Instead, there is the
possibility to have more that one trigger source enabled.

Internals:
- the acquisition metadata now provides a whiterabbit timestamp
  and information about the trigger source that started the acquisition

Registers change:
- one register to enable/disable all trigger sources
- one register to set the polarity on all the triggers
- threshould/hysteresis for each channel
- delay on the following triggers: ext, channel[1; 4]

Sysfs changes
- add attributes to configure threshould
- trigger "enable" will restore the last known enable status
parent 32ef6bfc
......@@ -411,19 +411,9 @@ static int __fa_init(struct fa_dev *fa)
/* Set to single shot mode by default */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_SHOTS_NB], 1);
if (zdev->cset->ti->cset->trig == &zfat_type) {
/* Select external trigger (index 0) */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_SEL],
1);
zdev->cset->ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_EXT].value = 1;
} else {
/* Enable Software trigger*/
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN],
1);
/* Disable Hardware trigger*/
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN],
0);
}
/* No trigger source enabled by default */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SRC], 0);
/* Zero offsets and release the DAC clear */
zfad_reset_offset(fa);
......@@ -436,7 +426,7 @@ static int __fa_init(struct fa_dev *fa)
fa_writel(fa, fa->fa_utc_base, &zfad_regs[ZFA_UTC_SECONDS],
get_seconds());
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_DLY], 0);
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_EXT_DLY], 0);
/* disable auto_start */
fa->enable_auto_start = 0;
......
......@@ -53,8 +53,7 @@ int zfad_dma_start(struct zio_cset *cset)
* Disable all triggers to prevent fires between
* different DMA transfers required for multi-shots
*/
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN], 0);
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN], 0);
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SRC], 0);
/* Fix dev_mem_addr in single-shot mode */
if (fa->n_shots == 1) {
......@@ -124,13 +123,16 @@ void zfad_dma_done(struct zio_cset *cset)
ctrl = zio_get_ctrl(block);
trig_timetag = (uint32_t *)(block->data + block->datalen
- FA_TRIG_TIMETAG_BYTES);
/* Timetag marker (metadata) used for debugging */
dev_dbg(fa->msgdev, "trig_timetag metadata of the shot %d"
" (expected value: 0x6fc8ad2d): 0x%x\n",
i, *trig_timetag);
ctrl->tstamp.secs = *(++trig_timetag);
ctrl->tstamp.ticks = *(++trig_timetag);
ctrl->tstamp.bins = *(++trig_timetag);
if (unlikely((*(trig_timetag + 1) >> 8) != 0xACCE55))
dev_err(fa->msgdev,
"Wrong acquisition TAG, expected 0xACCE55 but got 0x%X (0x%X)\n",
(*(trig_timetag + 1) >> 8), *trig_timetag);
ctrl->tstamp.secs = ((uint64_t)*(trig_timetag + 1) & 0xFF) << 32;
ctrl->tstamp.secs |= *(trig_timetag);
ctrl->tstamp.ticks = *(trig_timetag + 2);
ctrl->tstamp.bins = 0;
ctrl->attr_trigger.ext_val[FA100M14B4C_TATTR_STA]= *(trig_timetag + 3);
/* Acquisition start Timetag */
ctrl->attr_channel.ext_val[FA100M14B4C_DATTR_ACQ_START_S] =
......@@ -159,24 +161,8 @@ void zfad_dma_done(struct zio_cset *cset)
dev_dbg(fa->msgdev, "%i blocks transfered\n", fa->n_shots);
zio_trigger_data_done(cset);
/*
* we can safely re-enable triggers.
* Hardware trigger depends on the enable status
* of the trigger. Software trigger depends on the previous
* status taken form zio attributes (index 5 of extended one)
* If the user is using a software trigger, enable the software
* trigger.
*/
if (cset->trig == &zfat_type) {
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN],
(ti->flags & ZIO_STATUS ? 0 : 1));
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN],
ti->zattr_set.ext_zattr[6].value);
} else {
dev_dbg(fa->msgdev, "Software acquisition over\n");
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN],
1);
}
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SRC],
ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_SRC].value);
}
......
......@@ -17,68 +17,81 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFA_CTL_TRIG_LED] = {0x00, 0x00000040, 1},
[ZFA_CTL_ACQ_LED] = {0x00, 0x00000080, 1},
/* Status registers */
[ZFA_STA_FSM] = {0x04, 0x00000007, 1},
[ZFA_STA_FSM] = {0x04, 0x00000007, 1},
[ZFA_STA_SERDES_PLL] = {0x04, 0x00000008, 1},
[ZFA_STA_SERDES_SYNCED] = {0x04, 0x00000010, 1},
/* Trigger */
/* Config register */
[ZFAT_CFG_HW_SEL] = {0x08, 0x00000001, 1},
[ZFAT_CFG_HW_POL] = {0x08, 0x00000002, 1},
[ZFAT_CFG_HW_EN] = {0x08, 0x00000004, 1},
[ZFAT_CFG_SW_EN] = {0x08, 0x00000008, 1},
[ZFAT_CFG_INT_SEL] = {0x08, 0x00000030, 1},
[ZFAT_CFG_THRES_FILT] = {0x08, 0x0000FF00, 1},
[ZFAT_CFG_THRES] = {0x08, 0xFFFF0000, 1},
[ZFAT_CFG_STA] = {0x08, 0xFFFFFFFF, 0},
[ZFAT_CFG_SRC] = {0x0C, 0xFFFFFFFF, 0},
[ZFAT_CFG_POL] = {0x10, 0xFFFFFFFF, 0},
/* Delay */
[ZFAT_DLY] = {0x0C, 0xFFFFFFFF, 0},
[ZFAT_EXT_DLY] = {0x14, 0xFFFFFFFF, 0},
/* Software */
[ZFAT_SW] = {0x10, 0xFFFFFFFF, 0},
[ZFAT_SW] = {0x18, 0xFFFFFFFF, 0},
/* Number of shots */
[ZFAT_SHOTS_NB] = {0x14, 0x0000FFFF, 0},
[ZFAT_SHOTS_NB] = {0x1C, 0x0000FFFF, 0},
/* Multishot max samples*/
[ZFA_MULT_MAX_SAMP] = {0x20, 0xFFFFFFFF, 0},
/* Remaining shots counter */
[ZFAT_SHOTS_REM] = {0x18, 0x0000FFFF, 0},
[ZFAT_SHOTS_REM] = {0x24, 0x0000FFFF, 0},
/* Position address */
[ZFAT_POS] = {0x28, 0xFFFFFFFF, 0},
/* Sampling clock frequency */
[ZFAT_SAMPLING_HZ] = {0x20, 0xFFFFFFFF, 0},
[ZFAT_SAMPLING_HZ] = {0x2C, 0xFFFFFFFF, 0},
/* Sample rate */
[ZFAT_SR_UNDER] = {0x24, 0xFFFFFFFF, 0},
/* Position address */
[ZFAT_POS] = {0x1C, 0xFFFFFFFF, 0},
[ZFAT_SR_UNDER] = {0x30, 0xFFFFFFFF, 0},
/* Pre-sample */
[ZFAT_PRE] = {0x28, 0xFFFFFFFF, 0},
[ZFAT_PRE] = {0x34, 0xFFFFFFFF, 0},
/* Post-sample */
[ZFAT_POST] = {0x2C, 0xFFFFFFFF, 0},
[ZFAT_POST] = {0x38, 0xFFFFFFFF, 0},
/* Sample counter */
[ZFAT_CNT] = {0x30, 0xFFFFFFFF, 0},
[ZFAT_CNT] = {0x3C, 0xFFFFFFFF, 0},
/* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {0x34, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x34, 0x00000008, 1},
[ZFA_CH1_STA] = {0x38, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x3C, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x40, 0x0000FFFF, 0},
[ZFA_CH1_SAT] = {0x44, 0x00007FFF, 0},
[ZFA_CH1_CTL_RANGE] = {0x80, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x80, 0x00000008, 1},
[ZFA_CH1_STA] = {0x84, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x88, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x8C, 0x0000FFFF, 0},
[ZFA_CH1_SAT] = {0x90, 0x00007FFF, 0},
[ZFA_CH1_THRES] = {0x94, 0xFFFF0000, 1},
[ZFA_CH1_HYST] = {0x94, 0x0000FFFF, 1},
[ZFA_CH1_DLY] = {0x98, 0xFFFFFFFF, 0},
/* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {0x48, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x48, 0x00000008, 1},
[ZFA_CH2_STA] = {0x4C, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x50, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x54, 0x0000FFFF, 0},
[ZFA_CH2_SAT] = {0x58, 0x00007FFF, 0},
[ZFA_CH2_CTL_RANGE] = {0x100, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x100, 0x00000008, 1},
[ZFA_CH2_STA] = {0x104, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x108, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x10C, 0x0000FFFF, 0},
[ZFA_CH2_SAT] = {0x110, 0x00007FFF, 0},
[ZFA_CH2_THRES] = {0x114, 0xFFFF0000, 1},
[ZFA_CH2_HYST] = {0x114, 0x0000FFFF, 1},
[ZFA_CH2_DLY] = {0x118, 0xFFFFFFFF, 0},
/* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {0x5C, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x5C, 0x00000008, 1},
[ZFA_CH3_STA] = {0x60, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x64, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x68, 0x0000FFFF, 0},
[ZFA_CH3_SAT] = {0x6C, 0x00007FFF, 0},
[ZFA_CH3_CTL_RANGE] = {0x180, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x180, 0x00000008, 1},
[ZFA_CH3_STA] = {0x184, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x188, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x18C, 0x0000FFFF, 0},
[ZFA_CH3_SAT] = {0x190, 0x00007FFF, 0},
[ZFA_CH3_THRES] = {0x194, 0xFFFF0000, 1},
[ZFA_CH3_HYST] = {0x194, 0x0000FFFF, 1},
[ZFA_CH3_DLY] = {0x198, 0xFFFFFFFF, 0},
/* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {0x70, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x70, 0x00000008, 1},
[ZFA_CH4_STA] = {0x74, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x78, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x7C, 0x0000FFFF, 0},
[ZFA_CH4_SAT] = {0x80, 0x00007FFF, 0},
/* Other options */
[ZFA_MULT_MAX_SAMP] = {0x84, 0xFFFFFFFF, 0},
[ZFA_CH4_CTL_RANGE] = {0x200, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x200, 0x00000008, 1},
[ZFA_CH4_STA] = {0x204, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x208, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x20C, 0x0000FFFF, 0},
[ZFA_CH4_SAT] = {0x210, 0x00007FFF, 0},
[ZFA_CH4_THRES] = {0x214, 0xFFFF0000, 1},
[ZFA_CH4_HYST] = {0x214, 0x0000FFFF, 1},
[ZFA_CH4_DLY] = {0x218, 0xFFFFFFFF, 0},
/* IRQ */
[ZFA_IRQ_ADC_DISABLE_MASK] = {0x00, 0x00000003, 0},
[ZFA_IRQ_ADC_ENABLE_MASK] = {0x04, 0x00000003, 0},
......@@ -88,12 +101,13 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFA_IRQ_VIC_ENABLE_MASK] = {0x08, 0x00000003, 0},
[ZFA_IRQ_VIC_DISABLE_MASK] = {0x0C, 0x00000003, 0},
[ZFA_IRQ_VIC_MASK_STATUS] = {0x10, 0x00000003, 0},
/* UTC */
[ZFA_UTC_SECONDS] = {0x00, ~0x0, 0},
[ZFA_UTC_COARSE] = {0x04, ~0x0, 0},
[ZFA_UTC_TRIG_META] = {0x08, ~0x0, 0},
[ZFA_UTC_TRIG_SECONDS] = {0x0C, ~0x0, 0},
[ZFA_UTC_TRIG_COARSE] = {0x10, ~0x0, 0},
[ZFA_UTC_TRIG_COARSE] = {0x10, ~0x0, 0},
[ZFA_UTC_TRIG_FINE] = {0x14, ~0x0, 0},
[ZFA_UTC_ACQ_START_META] = {0x18, ~0x0, 0},
[ZFA_UTC_ACQ_START_SECONDS] = {0x1C, ~0x0, 0},
......
......@@ -30,43 +30,61 @@ static ZIO_ATTR_DEFINE_STD(ZIO_TRG, zfat_std_zattr) = {
ZIO_ATTR(trig, ZIO_ATTR_TRIG_POST_SAMP, ZIO_RW_PERM, ZFAT_POST, 1),
};
static struct zio_attribute zfat_ext_zattr[] = {
/* Config register */
/* Hardware trigger selction
* 0: internal (data threshold)
* 1: external (front panel trigger input)
*/
[FA100M14B4C_TATTR_EXT] = ZIO_ATTR_EXT("external", ZIO_RW_PERM,
ZFAT_CFG_HW_SEL, 0),
/*
* Internal Hardware trigger polarity
* 0: positive edge/slope
* 1: negative edge/slope
*/
[FA100M14B4C_TATTR_STA] = ZIO_ATTR_EXT("source-triggered", ZIO_RW_PERM,
ZFAT_CFG_STA, 0),
[FA100M14B4C_TATTR_SRC] = ZIO_ATTR_EXT("source", ZIO_RW_PERM,
ZFAT_CFG_SRC, 0),
[FA100M14B4C_TATTR_POL] = ZIO_ATTR_EXT("polarity", ZIO_RW_PERM,
ZFAT_CFG_HW_POL, 0),
/*
* Channel selection for internal trigger
* 0: channel 1, 1: channel 2, 2: channel 3, 3: channel 4
*/
[FA100M14B4C_TATTR_INT_CHAN] = ZIO_ATTR_EXT("int-channel",
ZIO_RW_PERM, ZFAT_CFG_INT_SEL, 0),
ZFAT_CFG_POL, 0),
/* Internal trigger threshold value is 2 complement format */
[FA100M14B4C_TATTR_INT_THRES] = ZIO_ATTR_EXT("int-threshold",
ZIO_RW_PERM, ZFAT_CFG_THRES, 0),
[FA100M14B4C_TATTR_CH1_THRES] = ZIO_ATTR_EXT("ch0-threshold",
ZIO_RW_PERM,
ZFA_CH1_THRES, 0),
[FA100M14B4C_TATTR_CH2_THRES] = ZIO_ATTR_EXT("ch1-threshold",
ZIO_RW_PERM,
ZFA_CH2_THRES, 0),
[FA100M14B4C_TATTR_CH3_THRES] = ZIO_ATTR_EXT("ch2-threshold",
ZIO_RW_PERM,
ZFA_CH3_THRES, 0),
[FA100M14B4C_TATTR_CH4_THRES] = ZIO_ATTR_EXT("ch3-threshold",
ZIO_RW_PERM,
ZFA_CH4_THRES, 0),
[FA100M14B4C_TATTR_CH1_HYST] = ZIO_ATTR_EXT("ch0-hysteresis",
ZIO_RW_PERM,
ZFA_CH1_HYST, 0),
[FA100M14B4C_TATTR_CH2_HYST] = ZIO_ATTR_EXT("ch1-hysteresis",
ZIO_RW_PERM,
ZFA_CH2_HYST, 0),
[FA100M14B4C_TATTR_CH3_HYST] = ZIO_ATTR_EXT("ch2-hysteresis",
ZIO_RW_PERM,
ZFA_CH3_HYST, 0),
[FA100M14B4C_TATTR_CH4_HYST] = ZIO_ATTR_EXT("ch3-hysteresis",
ZIO_RW_PERM,
ZFA_CH4_HYST, 0),
[FA100M14B4C_TATTR_CH1_DLY] = ZIO_ATTR_EXT("ch0-delay",
ZIO_RW_PERM,
ZFA_CH1_DLY, 0),
[FA100M14B4C_TATTR_CH2_DLY] = ZIO_ATTR_EXT("ch1-delay",
ZIO_RW_PERM,
ZFA_CH2_DLY, 0),
[FA100M14B4C_TATTR_CH3_DLY] = ZIO_ATTR_EXT("ch2-delay",
ZIO_RW_PERM,
ZFA_CH3_DLY, 0),
[FA100M14B4C_TATTR_CH4_DLY] = ZIO_ATTR_EXT("ch3-delay",
ZIO_RW_PERM,
ZFA_CH4_DLY, 0),
/*
* Delay to apply on the trigger in sampling clock period. The default
* clock frequency is 100MHz (period = 10ns)
*/
[FA100M14B4C_TATTR_DELAY] = ZIO_ATTR_EXT("delay", ZIO_RW_PERM,
ZFAT_DLY, 0),
[FA100M14B4C_TATTR_EXT_DLY] = ZIO_ATTR_EXT("ext-delay", ZIO_RW_PERM,
ZFAT_EXT_DLY, 0),
/* setup the maximum glith length to filter */
ZIO_ATTR_EXT("int-threshold-filter", ZIO_RW_PERM, ZFAT_CFG_THRES_FILT,
0),
/* Software Trigger */
/* Enable (1) or disable (0) software trigger */
[FA100M14B4C_TATTR_SW_EN] = ZIO_PARAM_EXT("sw-trg-enable", ZIO_RW_PERM,
ZFAT_CFG_SW_EN, 0),
[FA100M14B4C_TATTR_SW_FIRE] = ZIO_PARAM_EXT("sw-trg-fire", ZIO_WO_PERM,
ZFAT_SW, 0),
......@@ -108,7 +126,8 @@ static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
break;
case ZFAT_SW:
/* Fire if software trigger is enabled (index 5) */
if (!ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_SW_EN].value) {
if (!(ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_SRC].value &
FA100M14B4C_TRG_SRC_SW)) {
dev_info(fa->msgdev, "sw trigger is not enabled\n");
return -EPERM;
}
......@@ -123,6 +142,16 @@ static int zfat_conf_set(struct device *dev, struct zio_attribute *zattr,
* acquisition or other problems:
*/
break;
case ZFAT_CFG_SRC:
/*
* Do not copy to hardware when globally disabled
* We tell ZIO to save the value locally and will do
* it when the user starts an acquisition
*
* We cannot save the value in cache only when disabled
* because the trigger is always disabled during configuration
*/
return 0;
}
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[zattr->id], tmp_val);
......@@ -139,6 +168,15 @@ static int zfat_info_get(struct device *dev, struct zio_attribute *zattr,
{
struct fa_dev *fa = get_zfadc(dev);
switch (zattr->id) {
case ZFAT_CFG_SRC:
/*
* The good value for the trigger source is always in
* the ZIO cache.
*/
return 0;
}
*usr_val = fa_readl(fa, fa->fa_adc_csr_base, &zfad_regs[zattr->id]);
switch (zattr->id) {
case ZFAT_POST:
......@@ -172,11 +210,6 @@ static struct zio_ti *zfat_create(struct zio_trigger_type *trig,
if (!zfat)
return ERR_PTR(-ENOMEM);
/* Disable Software trigger*/
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN], 0);
/* Enable Hardware trigger*/
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN], 1);
zfat->fa = fa;
zfat->ti.cset = cset;
......@@ -188,10 +221,9 @@ static void zfat_destroy(struct zio_ti *ti)
struct fa_dev *fa = ti->cset->zdev->priv_d;
struct zfat_instance *zfat = to_zfat_instance(ti);
/* Enable Software trigger */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN], 1);
/* Disable Hardware trigger */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN], 0);
/* Disable all trigger sources */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SRC], 0);
/* Other triggers cannot use pre-samples */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_PRE], 0);
/* Reset post samples */
......@@ -204,15 +236,22 @@ static void zfat_destroy(struct zio_ti *ti)
/*
*
* Enable or disable the hardware trigger. The hardware trigger is the prefered
* trigger so it correspond to the ZIO enable of the trigger.Status is active
* low on ZIO but active high on the FMC-ADC, then use '!' on status
* Enable or disable the trigger sources globally.
* On disable (status > 0), we disable all the trigger sources
* On enable (status == 0), we enable the trigger soruces specified in the
* correspondent sysfs attribute
*/
static void zfat_change_status(struct zio_ti *ti, unsigned int status)
{
struct fa_dev *fa = ti->cset->zdev->priv_d;
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN], !status);
uint32_t src = ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_SRC].value;
if (status)
fa_writel(fa, fa->fa_adc_csr_base,
&zfad_regs[ZFAT_CFG_SRC], 0);
else
fa_writel(fa, fa->fa_adc_csr_base,
&zfad_regs[ZFAT_CFG_SRC], src);
}
/*
......@@ -273,7 +312,7 @@ static int zfat_arm_trigger(struct zio_ti *ti)
struct zio_block *block;
struct zfad_block *zfad_block;
unsigned int size;
uint32_t dev_mem_off;
uint32_t dev_mem_off, trg_src;
int i, err = 0;
dev_dbg(fa->msgdev, "Arming trigger\n");
......@@ -348,6 +387,10 @@ static int zfat_arm_trigger(struct zio_ti *ti)
if (err != -EAGAIN && err != 0)
goto out_allocate;
/* Everything looks fine for the time being, enable the trigger sources */
trg_src = ti->zattr_set.ext_zattr[FA100M14B4C_TATTR_SRC].value;
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SRC], trg_src);
return err;
out_allocate:
......
......@@ -12,6 +12,25 @@
#define BIT(nr) (1UL << (nr))
#endif
/* Trigger sources */
#define FA100M14B4C_TRG_SRC_EXT BIT(0)
#define FA100M14B4C_TRG_SRC_SW BIT(1)
#define FA100M14B4C_TRG_SRC_TIM BIT(4)
#define FA100M14B4C_TRG_SRC_CH1 BIT(8)
#define FA100M14B4C_TRG_SRC_CH2 BIT(9)
#define FA100M14B4C_TRG_SRC_CH3 BIT(10)
#define FA100M14B4C_TRG_SRC_CH4 BIT(11)
#define FA100M14B4C_TRG_SRC_CHx(_x) (FA100M14B4C_TRG_SRC_CH1 << ((_x) - 1))
/* Trigger Polarity */
#define FA100M14B4C_TRG_POL_EXT FA100M14B4C_TRG_SRC_EXT
#define FA100M14B4C_TRG_POL_CH1 FA100M14B4C_TRG_SRC_CH1
#define FA100M14B4C_TRG_POL_CH2 FA100M14B4C_TRG_SRC_CH2
#define FA100M14B4C_TRG_POL_CH3 FA100M14B4C_TRG_SRC_CH3
#define FA100M14B4C_TRG_POL_CH4 FA100M14B4C_TRG_SRC_CH4
#define FA100M14B4C_TRG_POL_CHx(_x) (FA100M14B4C_TRG_POL_CH1 << ((_x) - 1))
/*
* Trigger Extended Attribute Enumeration
*/
......@@ -24,13 +43,24 @@ enum fa100m14b4c_trg_ext_attr {
* The parameters are not exposed to user space by zio_controle, so it
* is not necessary to export to user space the correspondent enum
*/
FA100M14B4C_TATTR_EXT = 0,
FA100M14B4C_TATTR_STA = 0,
FA100M14B4C_TATTR_SRC,
FA100M14B4C_TATTR_POL,
FA100M14B4C_TATTR_INT_CHAN,
FA100M14B4C_TATTR_INT_THRES,
FA100M14B4C_TATTR_DELAY,
FA100M14B4C_TATTR_EXT_DLY,
FA100M14B4C_TATTR_CH1_THRES,
FA100M14B4C_TATTR_CH2_THRES,
FA100M14B4C_TATTR_CH3_THRES,
FA100M14B4C_TATTR_CH4_THRES,
FA100M14B4C_TATTR_CH1_HYST,
FA100M14B4C_TATTR_CH2_HYST,
FA100M14B4C_TATTR_CH3_HYST,
FA100M14B4C_TATTR_CH4_HYST,
FA100M14B4C_TATTR_CH1_DLY,
FA100M14B4C_TATTR_CH2_DLY,
FA100M14B4C_TATTR_CH3_DLY,
FA100M14B4C_TATTR_CH4_DLY,
#ifdef __KERNEL__
FA100M14B4C_TATTR_SW_EN,
FA100M14B4C_TATTR_SW_FIRE,
FA100M14B4C_TATTR_TRG_S,
FA100M14B4C_TATTR_TRG_C,
......@@ -115,7 +145,7 @@ enum fa100m14b4c_fsm_state {
* ZFA_CHx_MULT : the trick which requires channel regs id grouped and ordered
* address offset between two registers of the same type on consecutive channel
*/
#define ZFA_CHx_MULT 6
#define ZFA_CHx_MULT 9
/* Device registers */
enum zfadc_dregs_enum {
......@@ -133,15 +163,11 @@ enum zfadc_dregs_enum {
ZFA_STA_SERDES_PLL,
ZFA_STA_SERDES_SYNCED,
/* Configuration register */
ZFAT_CFG_HW_SEL,
ZFAT_CFG_HW_POL,
ZFAT_CFG_HW_EN,
ZFAT_CFG_SW_EN,
ZFAT_CFG_INT_SEL,
ZFAT_CFG_THRES,
ZFAT_CFG_THRES_FILT,
ZFAT_CFG_STA,
ZFAT_CFG_SRC,
ZFAT_CFG_POL,
/* Delay*/
ZFAT_DLY,
ZFAT_EXT_DLY,
/* Software */
ZFAT_SW,
/* Number of shots */
......@@ -168,6 +194,10 @@ enum zfadc_dregs_enum {
ZFA_CH1_GAIN,
ZFA_CH1_OFFSET,
ZFA_CH1_SAT,
ZFA_CH1_THRES,
ZFA_CH1_HYST,
ZFA_CH1_DLY,
/* Channel 2 */
ZFA_CH2_CTL_RANGE,
ZFA_CH2_CTL_TERM,
......@@ -175,6 +205,10 @@ enum zfadc_dregs_enum {
ZFA_CH2_GAIN,
ZFA_CH2_OFFSET,
ZFA_CH2_SAT,
ZFA_CH2_THRES,
ZFA_CH2_HYST,
ZFA_CH2_DLY,
/* Channel 3 */
ZFA_CH3_CTL_RANGE,
ZFA_CH3_CTL_TERM,
......@@ -182,6 +216,10 @@ enum zfadc_dregs_enum {
ZFA_CH3_GAIN,
ZFA_CH3_OFFSET,
ZFA_CH3_SAT,
ZFA_CH3_THRES,
ZFA_CH3_HYST,
ZFA_CH3_DLY,
/* Channel 4 */
ZFA_CH4_CTL_RANGE,
ZFA_CH4_CTL_TERM,
......@@ -189,6 +227,10 @@ enum zfadc_dregs_enum {
ZFA_CH4_GAIN,
ZFA_CH4_OFFSET,
ZFA_CH4_SAT,
ZFA_CH4_THRES,
ZFA_CH4_HYST,
ZFA_CH4_DLY,
/*
* CHx__ are specifc ids used by some internal arithmetic
* Be carefull: the arithmetic expects
......@@ -202,7 +244,9 @@ enum zfadc_dregs_enum {
ZFA_CHx_GAIN,
ZFA_CHx_OFFSET,
ZFA_CHx_SAT,
ZFA_CHx_THRES,
ZFA_CHx_HYST,
ZFA_CHx_DLY,
/* Other options */
ZFA_MULT_MAX_SAMP,
/* end:declaration block requiring some order */
......@@ -237,9 +281,11 @@ enum zfadc_dregs_enum {
ZFA_HW_PARAM_COMMON_LAST,
};
/* trigger timestamp block size in bytes */
/* This block is added after the post trigger samples */
/* in the DDR and contains the trigger timestamp */
/*
* Acquisition metadata. It contains the trigger timestamp and the trigger
* source. This block is added after the post-trigger-samples in the DDR.
*/
#define FA_TRIG_TIMETAG_BYTES 0x10
/*
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment