Commit ef1033e1 authored by Federico Vaga's avatar Federico Vaga

regtable: update registers eccording to gateware v4.0

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent a554f0f6
...@@ -26,7 +26,9 @@ const struct zfa_field_desc zfad_regs[] = { ...@@ -26,7 +26,9 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFAT_CFG_HW_POL] = {0x08, 0x00000002, 1}, [ZFAT_CFG_HW_POL] = {0x08, 0x00000002, 1},
[ZFAT_CFG_HW_EN] = {0x08, 0x00000004, 1}, [ZFAT_CFG_HW_EN] = {0x08, 0x00000004, 1},
[ZFAT_CFG_SW_EN] = {0x08, 0x00000008, 1}, [ZFAT_CFG_SW_EN] = {0x08, 0x00000008, 1},
[ZFAT_CFG_INT_SEL] = {0x08, 0x00000070, 1}, [ZFAT_CFG_INT_SEL] = {0x08, 0x00000030, 1},
[ZFAT_CFG_TEST_EN] = {0x08, 0x00000040, 1},
[ZFAT_CFG_THRES_FILT] = {0x08, 0x0000FF00, 1},
[ZFAT_CFG_THRES] = {0x08, 0xFFFF0000, 1}, [ZFAT_CFG_THRES] = {0x08, 0xFFFF0000, 1},
/* Delay */ /* Delay */
[ZFAT_DLY] = {0x0C, 0xFFFFFFFF, 0}, [ZFAT_DLY] = {0x0C, 0xFFFFFFFF, 0},
...@@ -34,40 +36,48 @@ const struct zfa_field_desc zfad_regs[] = { ...@@ -34,40 +36,48 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFAT_SW] = {0x10, 0xFFFFFFFF, 0}, [ZFAT_SW] = {0x10, 0xFFFFFFFF, 0},
/* Number of shots */ /* Number of shots */
[ZFAT_SHOTS_NB] = {0x14, 0x0000FFFF, 0}, [ZFAT_SHOTS_NB] = {0x14, 0x0000FFFF, 0},
/* Remaining shots counter */
[ZFAT_SHOTS_REM] = {0x18, 0x0000FFFF, 0},
/* Sampling clock frequency */
[ZFAT_SAMPLING_HZ] = {0x20, 0xFFFFFFFF, 0},
/* Sample rate */ /* Sample rate */
[ZFAT_SR_DECI] = {0x1C, 0xFFFFFFFF, 0}, [ZFAT_SR_DECI] = {0x24, 0xFFFFFFFF, 0},
/* Position address */ /* Position address */
[ZFAT_POS] = {0x18, 0xFFFFFFFF, 0}, [ZFAT_POS] = {0x1C, 0xFFFFFFFF, 0},
/* Pre-sample */ /* Pre-sample */
[ZFAT_PRE] = {0x20, 0xFFFFFFFF, 0}, [ZFAT_PRE] = {0x28, 0xFFFFFFFF, 0},
/* Post-sample */ /* Post-sample */
[ZFAT_POST] = {0x24, 0xFFFFFFFF, 0}, [ZFAT_POST] = {0x2C, 0xFFFFFFFF, 0},
/* Sample counter */ /* Sample counter */
[ZFAT_CNT] = {0x28, 0xFFFFFFFF, 0}, [ZFAT_CNT] = {0x30, 0xFFFFFFFF, 0},
/* Channel 1 */ /* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {0x2C, 0x00000077, 1}, [ZFA_CH1_CTL_RANGE] = {0x34, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x2C, 0x00000008, 1}, [ZFA_CH1_CTL_TERM] = {0x34, 0x00000008, 1},
[ZFA_CH1_STA] = {0x30, 0x0000FFFF, 0}, [ZFA_CH1_STA] = {0x38, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x34, 0x0000FFFF, 0}, [ZFA_CH1_GAIN] = {0x3C, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x38, 0x0000FFFF, 0}, [ZFA_CH1_OFFSET] = {0x40, 0x0000FFFF, 0},
[ZFA_CH1_SAT] = {0x44, 0x00007FFF, 0},
/* Channel 2 */ /* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {0x3C, 0x00000077, 1}, [ZFA_CH2_CTL_RANGE] = {0x48, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x3C, 0x00000008, 1}, [ZFA_CH2_CTL_TERM] = {0x48, 0x00000008, 1},
[ZFA_CH2_STA] = {0x40, 0x0000FFFF, 0}, [ZFA_CH2_STA] = {0x4C, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x44, 0x0000FFFF, 0}, [ZFA_CH2_GAIN] = {0x50, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x48, 0x0000FFFF, 0}, [ZFA_CH2_OFFSET] = {0x54, 0x0000FFFF, 0},
[ZFA_CH2_SAT] = {0x58, 0x00007FFF, 0},
/* Channel 3 */ /* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {0x4C, 0x00000077, 1}, [ZFA_CH3_CTL_RANGE] = {0x5C, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x4C, 0x00000008, 1}, [ZFA_CH3_CTL_TERM] = {0x5C, 0x00000008, 1},
[ZFA_CH3_STA] = {0x50, 0x0000FFFF, 0}, [ZFA_CH3_STA] = {0x60, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x54, 0x0000FFFF, 0}, [ZFA_CH3_GAIN] = {0x64, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x58, 0x0000FFFF, 0}, [ZFA_CH3_OFFSET] = {0x68, 0x0000FFFF, 0},
[ZFA_CH3_SAT] = {0x6C, 0x00007FFF, 0},
/* Channel 4 */ /* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {0x5C, 0x00000077, 1}, [ZFA_CH4_CTL_RANGE] = {0x70, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x5C, 0x00000008, 1}, [ZFA_CH4_CTL_TERM] = {0x70, 0x00000008, 1},
[ZFA_CH4_STA] = {0x60, 0x0000FFFF, 0}, [ZFA_CH4_STA] = {0x74, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x64, 0x0000FFFF, 0}, [ZFA_CH4_GAIN] = {0x78, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x68, 0x0000FFFF, 0}, [ZFA_CH4_OFFSET] = {0x7C, 0x0000FFFF, 0},
[ZFA_CH4_SAT] = {0x80, 0x00007FFF, 0},
/* IRQ */ /* IRQ */
[ZFA_IRQ_ADC_DISABLE_MASK] = {0x00, 0x00000003, 0}, [ZFA_IRQ_ADC_DISABLE_MASK] = {0x00, 0x00000003, 0},
[ZFA_IRQ_ADC_ENABLE_MASK] = {0x04, 0x00000003, 0}, [ZFA_IRQ_ADC_ENABLE_MASK] = {0x04, 0x00000003, 0},
......
...@@ -134,14 +134,20 @@ enum zfadc_dregs_enum { ...@@ -134,14 +134,20 @@ enum zfadc_dregs_enum {
ZFAT_CFG_SW_EN, ZFAT_CFG_SW_EN,
ZFAT_CFG_INT_SEL, ZFAT_CFG_INT_SEL,
ZFAT_CFG_THRES, ZFAT_CFG_THRES,
ZFAT_CFG_TEST_EN,
ZFAT_CFG_THRES_FILT,
/* Delay*/ /* Delay*/
ZFAT_DLY, ZFAT_DLY,
/* Software */ /* Software */
ZFAT_SW, ZFAT_SW,
/* Number of shots */ /* Number of shots */
ZFAT_SHOTS_NB, ZFAT_SHOTS_NB,
/* Remaining shots counter */
ZFAT_SHOTS_REM,
/* Sample rate */ /* Sample rate */
ZFAT_SR_DECI, ZFAT_SR_DECI,
/* Sampling clock frequency */
ZFAT_SAMPLING_HZ,
/* Position address */ /* Position address */
ZFAT_POS, ZFAT_POS,
/* Pre-sample */ /* Pre-sample */
...@@ -157,24 +163,28 @@ enum zfadc_dregs_enum { ...@@ -157,24 +163,28 @@ enum zfadc_dregs_enum {
ZFA_CH1_STA, ZFA_CH1_STA,
ZFA_CH1_GAIN, ZFA_CH1_GAIN,
ZFA_CH1_OFFSET, ZFA_CH1_OFFSET,
ZFA_CH1_SAT,
/* Channel 2 */ /* Channel 2 */
ZFA_CH2_CTL_RANGE, ZFA_CH2_CTL_RANGE,
ZFA_CH2_CTL_TERM, ZFA_CH2_CTL_TERM,
ZFA_CH2_STA, ZFA_CH2_STA,
ZFA_CH2_GAIN, ZFA_CH2_GAIN,
ZFA_CH2_OFFSET, ZFA_CH2_OFFSET,
ZFA_CH2_SAT,
/* Channel 3 */ /* Channel 3 */
ZFA_CH3_CTL_RANGE, ZFA_CH3_CTL_RANGE,
ZFA_CH3_CTL_TERM, ZFA_CH3_CTL_TERM,
ZFA_CH3_STA, ZFA_CH3_STA,
ZFA_CH3_GAIN, ZFA_CH3_GAIN,
ZFA_CH3_OFFSET, ZFA_CH3_OFFSET,
ZFA_CH3_SAT,
/* Channel 4 */ /* Channel 4 */
ZFA_CH4_CTL_RANGE, ZFA_CH4_CTL_RANGE,
ZFA_CH4_CTL_TERM, ZFA_CH4_CTL_TERM,
ZFA_CH4_STA, ZFA_CH4_STA,
ZFA_CH4_GAIN, ZFA_CH4_GAIN,
ZFA_CH4_OFFSET, ZFA_CH4_OFFSET,
ZFA_CH4_SAT,
/* /*
* CHx__ are specifc ids used by some internal arithmetic * CHx__ are specifc ids used by some internal arithmetic
* Be carefull: the arithmetic expects * Be carefull: the arithmetic expects
......
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