...
 
Commits (4)
......@@ -48,6 +48,7 @@ static int sg_alloc_table_from_pages_no_squash(struct sg_table *sgt,
unsigned int n_pages,
unsigned int offset,
unsigned long size,
unsigned int max_segment,
gfp_t gfp_mask)
{
struct scatterlist *sg;
......@@ -353,13 +354,13 @@ int zfad_fsm_command(struct fa_dev *fa, uint32_t command)
return -EIO;
}
dev_dbg(fa->msgdev, "FSM START Command, Enable interrupts\n");
dev_dbg(fa->msgdev, "FSM START Command\n");
fa_enable_irqs(fa);
fa_writel(fa, fa->fa_adc_csr_base,
&zfad_regs[ZFA_CTL_RST_TRG_STA], 1);
} else {
dev_dbg(fa->msgdev, "FSM STOP Command, Disable interrupts\n");
dev_dbg(fa->msgdev, "FSM STOP Command\n");
fa->enable_auto_start = 0;
fa_disable_irqs(fa);
}
......@@ -510,7 +511,7 @@ int fa_probe(struct platform_device *pdev)
case ADC_VER_SPEC:
memops.read = ioread32;
memops.write = iowrite32;
fa->sg_alloc_table_from_pages = sg_alloc_table_from_pages;
fa->sg_alloc_table_from_pages = __sg_alloc_table_from_pages;
break;
case ADC_VER_SVEC:
memops.read = ioread32be;
......
......@@ -306,6 +306,7 @@ static int zfad_dma_prep_slave_sg(struct dma_chan *dchan,
struct dma_async_tx_descriptor *tx;
struct page **pages;
unsigned int nr_pages, sg_mapped;
size_t max_segment_size;
int err;
/* prepare the context for the block transfer */
......@@ -323,9 +324,11 @@ static int zfad_dma_prep_slave_sg(struct dma_chan *dchan,
goto err_to_pages;
/* With some version we cannot use the version from the Linux kernel */
max_segment_size = dma_get_max_seg_size(dchan->device->dev);
fa->sg_alloc_table_from_pages(&zfad_block->sgt, pages, nr_pages,
offset_in_page(zfad_block->block->data),
zfad_block->block->datalen, GFP_KERNEL);
zfad_block->block->datalen,
max_segment_size, GFP_KERNEL);
if (unlikely(err))
goto err_sgt;
......
......@@ -14,7 +14,6 @@
#include <linux/interrupt.h>
#include "fmc-adc-100m14b4cha.h"
#include "fa-spec.h"
/*
* fat_get_irq_status
......@@ -65,9 +64,9 @@ irqreturn_t fa_irq_handler(int irq, void *arg)
if (!status)
return IRQ_NONE; /* No interrupt fired by this mezzanine */
dev_dbg(fa->msgdev, "Handle ADC interrupts\n");
if (status & FA_IRQ_ADC_ACQ_END) {
dev_dbg(fa->msgdev, "Handle ADC interrupts\n");
/*
* Acquiring samples is a critical section
* protected against any concurrent abbort trigger.
......@@ -142,8 +141,6 @@ int fa_free_irqs(struct fa_dev *fa)
int fa_enable_irqs(struct fa_dev *fa)
{
dev_dbg(fa->msgdev, "Enable interrupts\n");
fa_writel(fa, fa->fa_irq_adc_base,
&zfad_regs[ZFA_IRQ_ADC_ENABLE_MASK],
FA_IRQ_ADC_ACQ_END);
......@@ -152,8 +149,6 @@ int fa_enable_irqs(struct fa_dev *fa)
int fa_disable_irqs(struct fa_dev *fa)
{
dev_dbg(fa->msgdev, "Disable interrupts\n");
fa_writel(fa, fa->fa_irq_adc_base,
&zfad_regs[ZFA_IRQ_ADC_DISABLE_MASK],
FA_IRQ_ADC_ACQ_END);
......
......@@ -32,67 +32,67 @@ const struct zfa_field_desc zfad_regs[] = {
/* Software */
[ZFAT_SW] = {0x18, 0xFFFFFFFF, 0},
/* Number of shots */
[ZFAT_SHOTS_NB] = {0x1C, 0x0000FFFF, 0},
[ZFAT_SHOTS_NB] = {0x1C, 0x0000FFFF, 1},
/* Remaining shots counter */
[ZFAT_SHOTS_REM] = {0x1C, 0xFFFF0000, 1},
/* Multishot max samples*/
[ZFA_MULT_MAX_SAMP] = {0x20, 0xFFFFFFFF, 0},
/* Remaining shots counter */
[ZFAT_SHOTS_REM] = {0x24, 0x0000FFFF, 0},
/* Position address */
[ZFAT_POS] = {0x28, 0xFFFFFFFF, 0},
[ZFAT_POS] = {0x24, 0xFFFFFFFF, 0},
/* Sampling clock frequency */
[ZFAT_SAMPLING_HZ] = {0x2C, 0xFFFFFFFF, 0},
[ZFAT_SAMPLING_HZ] = {0x28, 0xFFFFFFFF, 0},
/* Sample rate */
[ZFAT_SR_UNDER] = {0x30, 0xFFFFFFFF, 0},
[ZFAT_SR_UNDER] = {0x2C, 0xFFFFFFFF, 0},
/* Pre-sample */
[ZFAT_PRE] = {0x34, 0xFFFFFFFF, 0},
[ZFAT_PRE] = {0x30, 0xFFFFFFFF, 0},
/* Post-sample */
[ZFAT_POST] = {0x38, 0xFFFFFFFF, 0},
[ZFAT_POST] = {0x34, 0xFFFFFFFF, 0},
/* Sample counter */
[ZFAT_CNT] = {0x3C, 0xFFFFFFFF, 0},
[ZFAT_CNT] = {0x38, 0xFFFFFFFF, 0},
/* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {0x80, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x80, 0x00000008, 1},
[ZFA_CH1_STA] = {0x84, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x88, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x8C, 0x0000FFFF, 0},
[ZFA_CH1_SAT] = {0x90, 0x00007FFF, 0},
[ZFA_CH1_HYST] = {0x94, 0xFFFF0000, 1},
[ZFA_CH1_THRES] = {0x94, 0x0000FFFF, 1},
[ZFA_CH1_DLY] = {0x98, 0xFFFFFFFF, 0},
[ZFA_CH1_GAIN] = {0x88, 0x0000FFFF, 1},
[ZFA_CH1_OFFSET] = {0x88, 0xFFFF0000, 1},
[ZFA_CH1_SAT] = {0x8C, 0x00007FFF, 0},
[ZFA_CH1_HYST] = {0x90, 0xFFFF0000, 1},
[ZFA_CH1_THRES] = {0x90, 0x0000FFFF, 1},
[ZFA_CH1_DLY] = {0x94, 0xFFFFFFFF, 0},
/* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {0x100, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x100, 0x00000008, 1},
[ZFA_CH2_STA] = {0x104, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x108, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x10C, 0x0000FFFF, 0},
[ZFA_CH2_SAT] = {0x110, 0x00007FFF, 0},
[ZFA_CH2_HYST] = {0x114, 0xFFFF0000, 1},
[ZFA_CH2_THRES] = {0x114, 0x0000FFFF, 1},
[ZFA_CH2_DLY] = {0x118, 0xFFFFFFFF, 0},
[ZFA_CH2_CTL_RANGE] = {0xC0, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0xC0, 0x00000008, 1},
[ZFA_CH2_STA] = {0xC4, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0xC8, 0x0000FFFF, 1},
[ZFA_CH2_OFFSET] = {0xC8, 0xFFFF0000, 1},
[ZFA_CH2_SAT] = {0xCC, 0x00007FFF, 0},
[ZFA_CH2_HYST] = {0xD0, 0xFFFF0000, 1},
[ZFA_CH2_THRES] = {0xD0, 0x0000FFFF, 1},
[ZFA_CH2_DLY] = {0xD4, 0xFFFFFFFF, 0},
/* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {0x180, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x180, 0x00000008, 1},
[ZFA_CH3_STA] = {0x184, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x188, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x18C, 0x0000FFFF, 0},
[ZFA_CH3_SAT] = {0x190, 0x00007FFF, 0},
[ZFA_CH3_HYST] = {0x194, 0xFFFF0000, 1},
[ZFA_CH3_THRES] = {0x194, 0x0000FFFF, 1},
[ZFA_CH3_DLY] = {0x198, 0xFFFFFFFF, 0},
[ZFA_CH3_CTL_RANGE] = {0x100, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x100, 0x00000008, 1},
[ZFA_CH3_STA] = {0x104, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x108, 0x0000FFFF, 1},
[ZFA_CH3_OFFSET] = {0x108, 0xFFFF0000, 1},
[ZFA_CH3_SAT] = {0x10C, 0x00007FFF, 0},
[ZFA_CH3_HYST] = {0x110, 0xFFFF0000, 1},
[ZFA_CH3_THRES] = {0x110, 0x0000FFFF, 1},
[ZFA_CH3_DLY] = {0x114, 0xFFFFFFFF, 0},
/* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {0x200, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x200, 0x00000008, 1},
[ZFA_CH4_STA] = {0x204, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x208, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x20C, 0x0000FFFF, 0},
[ZFA_CH4_SAT] = {0x210, 0x00007FFF, 0},
[ZFA_CH4_HYST] = {0x214, 0xFFFF0000, 1},
[ZFA_CH4_THRES] = {0x214, 0x0000FFFF, 1},
[ZFA_CH4_DLY] = {0x218, 0xFFFFFFFF, 0},
[ZFA_CH4_CTL_RANGE] = {0x140, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x140, 0x00000008, 1},
[ZFA_CH4_STA] = {0x144, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x148, 0x0000FFFF, 1},
[ZFA_CH4_OFFSET] = {0x148, 0xFFFF0000, 1},
[ZFA_CH4_SAT] = {0x14C, 0x00007FFF, 0},
[ZFA_CH4_HYST] = {0x150, 0xFFFF0000, 1},
[ZFA_CH4_THRES] = {0x150, 0x0000FFFF, 1},
[ZFA_CH4_DLY] = {0x154, 0xFFFFFFFF, 0},
/* IRQ */
[ZFA_IRQ_ADC_DISABLE_MASK] = {0x00, 0x00000003, 0},
......
......@@ -451,6 +451,7 @@ struct fa_dev {
unsigned int n_pages,
unsigned int offset,
unsigned long size,
unsigned int max_segment,
gfp_t gfp_mask);
};
......
......@@ -50,7 +50,8 @@ int fa_spi_xfer(struct fa_dev *fa, int cs, int num_bits,
while (fa_ioread(fa, fa->fa_spi_base + FA_SPI_CTRL)
& FA_SPI_CTRL_BUSY) {
if (jiffies > j) {
dev_err(fa->msgdev, "SPI transfer error\n");
dev_err(fa->msgdev, "SPI transfer error cs:%d, ctrl: 0x%x\n",
cs, fa_ioread(fa, fa->fa_spi_base + FA_SPI_CTRL));
err = -EIO;
goto out;
}
......