#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org

import sys
import rr
import time
import os
from numpy import *

from ptsexcept import *

import spec_fmc_adc
import fmc_adc
import calibr_box
import find_usb_tty
from PAGE.Agilent33250A import *
from PAGE.SineWaveform import *


"""
test08: Test analogue front-end switches

Note: Requires test00.py to run first to load the firmware!
"""


# Calibration box vendor and product IDs
BOX_USB_VENDOR_ID = 0x10c4 # Cygnal Integrated Products, Inc.
BOX_USB_PRODUCT_ID = 0xea60 # CP210x Composite Device
# Agilent AWG serial access vendor and product IDs
AWG_USB_VENDOR_ID = 0x0403 # Future Technology Devices International, Ltd
AWG_USB_PRODUCT_ID = 0x6001 # FT232 USB-Serial (UART) IC

AWG_BAUD = 57600

NB_CHANNELS = 4

PRE_TRIG_SAMPLES = 1000
POST_TRIG_SAMPLES = 100000
NB_SHOTS = 1

ACQ_LENGTH = 50000 # in samples
ACQ_TIMEOUT = 10

AWG_SET_SLEEP = 1
SSR_SET_SLEEP = 0.05
BOX_SET_SLEEP = 1

ADC_MID_VALUE = 0
ADC_MID_TOL = 500

SW1_TOL = 30000
SW2_TOL = 5000
SW3_TOL = 5000
SW4_TOL = 10000
SW5_TOL = 100
SW6_TOL = 20000
SW7_TOL = 20000


def hex2signed(value):
    if(value & 0x8000):
        return -((~value & 0xFFFF) + 1)
    else:
        return value

def acq_config(fmc):
    print('Initialise FMC board\n')
    # Set trigger
    fmc.set_soft_trig()
    # Set acquisition
    fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
    fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
    fmc.set_shots(NB_SHOTS)

def get_channels_mean(fmc, spec_fmc):
    # Make sure no acquisition is running
    fmc.stop_acq()
    # Start acquisition
    fmc.start_acq()
    time.sleep(0.01)
    # Trigger
    fmc.sw_trig()
    # Wait end of acquisition
    timeout = 0
    while('IDLE' != fmc.get_acq_fsm_state()):
        time.sleep(.1)
        timeout += 1
        if(ACQ_TIMEOUT < timeout):
            print "Acquisition timeout. Missing trigger?."
            print "Acq FSm state: %s"%fmc.get_acq_fsm_state()
            return 1
    # Retrieve data trough DMA
    trig_pos = fmc.get_trig_pos()
    # Enable "DMA done" iinterrupt
    spec_fmc.set_irq_en_mask(0x1)
    # Read ACQ_LENGTH samples after the trigger for all channels
    channels_data = spec_fmc.get_data((trig_pos<<3), ACQ_LENGTH*8)
    # Disable "DMA done" iinterrupt
    spec_fmc.set_irq_en_mask(0x0)
    channels_data = [hex2signed(item) for item in channels_data]
    # calculate mean value for each channel
    channels_mean = []
    for channel in range(1,NB_CHANNELS+1):
        channels_mean.append(mean(channels_data[channel-1::4]))
    return channels_mean

def set_awg_offset(gen, sine, offset):
    sine.dc = offset
    gen.play(sine)
    time.sleep(AWG_SET_SLEEP)

def print_current_adc_value(fmc, channel, file):
    adc_value = fmc.get_current_adc_value(channel)
    print('CH%d ADC value:0x%.4X  %d') % (channel, adc_value, adc_value)
    file.write('CH%d: 0x%.4X %d\n' % (channel, adc_value, adc_value))

# Routine to test SSR (Solid State Relay)
# Basic operation: Set AWG DC offset and SSRs -> read ADC value, change 1 SSR -> read ADC -> check ADC values difference
# Options: retry -> run the same test several times
#          threshold -> minimum number of try to pass the test
def sw_test(box, gen, sine, awg_offset, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_tol):
    print('\nTesting switch %d\n-------------------------')%sw
    set_awg_offset(gen, sine, awg_offset)
    print('AWG offset: %1.3fV') % awg_offset

    error = 0
    for i in range(1,NB_CHANNELS+1):
        pass_nb = 0
        box.select_output_ch(i) # connect AWG to current channel
        time.sleep(BOX_SET_SLEEP)
        fmc.set_ssr(i,ssr_1)
        time.sleep(SSR_SET_SLEEP)
        adc_value_before = get_channels_mean(fmc, spec_fmc)[i-1]
        fmc.set_ssr(i,ssr_2)
        time.sleep(SSR_SET_SLEEP)
        adc_value = get_channels_mean(fmc, spec_fmc)[i-1]
        diff = adc_value_before-adc_value
        print('CH%d ssr=0x%.2X: %6d  ssr=0x%.2X: %6d  diff:%6d ,min_diff:%6d') % (i, ssr_1, adc_value_before, ssr_2, adc_value, abs(diff), diff_tol)
        if(diff_tol > abs(diff)):
            print('#### SW%d of channel %d is malfunctioning') % (sw, i)
            #raise PtsError('SW%d of channel %d is malfunctioning' % (sw, i))
            error += 1
        fmc.set_ssr(i,0x0)
        time.sleep(SSR_SET_SLEEP)
    return error

def adc_mid_test(spec_fmc, fmc, tol):
    print('\nTesting ADC middle scale, all switches opened.\n-------------------------')

    error = 0
    for i in range(1,NB_CHANNELS+1):
        ssr_1 = 0x0
        fmc.set_ssr(i,ssr_1)
        time.sleep(SSR_SET_SLEEP)
        diff = get_channels_mean(fmc, spec_fmc)[i-1]
        print('CH%d ssr=0x%.2X, value:%6d, expected value: %d, diff:%6d, tolerence:%d') % (i, ssr_1, diff, ADC_MID_VALUE, diff, tol)
        if(abs(diff) > tol):
            print('#### One of channel %d switches is malfunctioning') % i
            #raise PtsError('One of channel %d switches is malfunctioning' % i)
            error += 1
    return error


def main (default_directory='.'):

    """
    path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
    path_firmware = '../firmwares/spec_fmcadc100m14b4cha.bin';

    firmware_loader = os.path.join(default_directory, path_fpga_loader)
    bitstream = os.path.join(default_directory, path_firmware)
    print firmware_loader + ' ' + bitstream
    os.system( firmware_loader + ' ' + bitstream )

    time.sleep(2);
    """

    # Objects declaration
    spec = rr.Gennum() # bind to the SPEC board
    spec_fmc = spec_fmc_adc.CSpecFmcAdc100Ms(spec)
    fmc = fmc_adc.CFmcAdc100Ms(spec)
    usb_tty = find_usb_tty.CttyUSB()
    awg_tty = usb_tty.find_usb_tty(AWG_USB_VENDOR_ID, AWG_USB_PRODUCT_ID)
    box_tty = usb_tty.find_usb_tty(BOX_USB_VENDOR_ID, BOX_USB_PRODUCT_ID)
    gen = Agilent33250A(device=awg_tty[0], bauds=AWG_BAUD)
    sine = SineWaveform()
    box = calibr_box.CCalibr_box(box_tty[0])

    # Set sine params -> ~ DC level
    sine.frequency = 0.000001
    sine.amplitude = 0.001
    sine.dc = 1

    # Set AWG and turn it ON
    gen.connect()
    gen.output = True

    # Configure acquisition
    acq_config(fmc)

    # Reset offset DACs to mid-scale (no offset)
    fmc.dc_offset_reset()

    # Uncomment the fillowing pblock to check calibration box output connections
    """
    print "Ckecking calibration box output connections"
    set_awg_offset(gen, sine, 2)
    for i in range(1,NB_CHANNELS+1):
        print "Channel %d"%i
        fmc.set_ssr(i,0x1)
        time.sleep(SSR_SET_SLEEP)
        box.select_output_ch(i) # connect AWG to current channel
        time.sleep(BOX_SET_SLEEP)
        print get_channels_mean(fmc, spec_fmc)
        fmc.set_ssr(i,0x0)
        time.sleep(SSR_SET_SLEEP)
    """

    # Test switches
    error = 0

    error += adc_mid_test(spec_fmc, fmc, ADC_MID_TOL)

    error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 1, 0x00, 0x01, SW1_TOL)
    error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 4, 0x01, 0x09, SW4_TOL)
    error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 5, 0x41, 0x51, SW5_TOL)
    error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 6, 0x00, 0x60, SW6_TOL)
    error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 7, 0x01, 0x41, SW7_TOL)
    error += sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 2, 0x20, 0x22, SW2_TOL)
    error += sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 3, 0x22, 0x26, SW3_TOL)

    # Make sure all switches are OFF
    for i in range(1,NB_CHANNELS+1):
        fmc.set_ssr(i,0x00)

    # Switch AWG OFF
    gen.output = False
    gen.close()

    # Check if an error occured during switches test
    if(error != 0):
        raise PtsError('An error occured during switches test, check log for details.')
    else:
        print "\nAll switches are working fine!"


    # Following commented code scan all SSR configurations to find good ones for testing switches
    """
    file = open("adc_analogue_test.txt", 'w')

    offset = 1
    set_awg_offset(gen, sine, offset)
    print('\nAWG offset: %f') % offset
    file.write('\n\nAWG offset: %f' % offset)

    for ssr in range(0x80):
        print('\nSSR: %.2X') % ssr
        file.write('\nSSR: %.2X\n' % ssr)
        for i in range(1,NB_CHANNELS+1):
            fmc.set_ssr(i,ssr)
            time.sleep(0.05)
            print_current_adc_value(fmc, i, file)
            fmc.set_ssr(i,0x0)
            time.sleep(0.05)


    offset = 0.5
    set_awg_offset(gen, sine, offset)
    print('\nAWG offset: %f') % offset
    file.write('\n\nAWG offset: %f' % offset)

    for ssr in range(0x80):
        print('\nSSR: %.2X') % ssr
        file.write('\nSSR: %.2X\n' % ssr)
        for i in range(1,NB_CHANNELS+1):
            fmc.set_ssr(i,ssr)
            time.sleep(0.05)
            print_current_adc_value(fmc, i, file)
            fmc.set_ssr(i,0x0)
            time.sleep(0.05)


    offset = 0.01
    set_awg_offset(gen, sine, offset)
    print('\nAWG offset: %f') % offset
    file.write('\n\nAWG offset: %f' % offset)

    for ssr in range(0x80):
        print('\nSSR: %.2X') % ssr
        file.write('\nSSR: %.2X\n' % ssr)
        for i in range(1,NB_CHANNELS+1):
            fmc.set_ssr(i,ssr)
            time.sleep(0.05)
            print_current_adc_value(fmc, i, file)
            fmc.set_ssr(i,0x0)
            time.sleep(0.05)


    offset = 0.25
    set_awg_offset(gen, sine, offset)
    print('\nAWG offset: %f') % offset
    file.write('\n\nAWG offset: %f' % offset)

    for ssr in range(0x80):
        print('\nSSR: %.2X') % ssr
        file.write('\nSSR: %.2X\n' % ssr)
        for i in range(1,NB_CHANNELS+1):
            fmc.set_ssr(i,ssr)
            time.sleep(0.05)
            print_current_adc_value(fmc, i, file)
            fmc.set_ssr(i,0x0)
            time.sleep(0.05)


    gen.output = False
    gen.close()
    sys.exit()
    """

    # Following commented code is for testing the tests
    """
    sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 1, 0x00, 0x00, SW1_TOL)
    sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 4, 0x01, 0x01, SW4_TOL)
    sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 5, 0x41, 0x41, SW5_TOL)
    sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 6, 0x00, 0x00, SW6_TOL)
    sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 7, 0x01, 0x01, SW7_TOL)
    sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 2, 0x20, 0x20, SW2_TOL)
    sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 3, 0x22, 0x22, SW3_TOL)
    """


if __name__ == '__main__' :
    main()
