Commit 033ed11b authored by Matthieu Cattin's avatar Matthieu Cattin

fmc_adc_spec/svec: Remove the mezzanine reset release (unactive by default in gw).

parent 63746a35
......@@ -77,10 +77,6 @@ class CFmcAdc100mSpec:
if(ct == 0xFFFFFFFF):
raise FmcAdc100mSpecOperationError("Bitstream not properly loaded.")
# Release the mezzanine software reset
self.set_sw_rst(1)
time.sleep(0.001) # gives time for ddr core to calibrates
# Configure VIC
#self.vic.print_regs()
self.vic.set_polarity(1) # output active high
......
......@@ -69,11 +69,6 @@ class CFmcAdc100mSvec:
if(ct == 0xFFFFFFFF):
raise FmcAdc100mSvecOperationError("Bitstream not properly loaded.")
# Release the mezzanines software reset
self.set_sw_rst(0,1)
self.set_sw_rst(1,1)
time.sleep(0.001) # gives time for ddr core to calibrates
# Configure VIC
#self.vic.print_regs()
self.vic.set_polarity(1) # output active high
......
......@@ -25,7 +25,7 @@ CARRIER_CSR=['Carrier control and status registers',{
'LED':[0, 'Front panel LEDs', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'RST':[0x0C, 'Reset', {
'FMC0':[0, 'FMC 1 software reset', 0x1],
'FMC1':[1, 'FMC 2 software reset', 0x1],
'FMC0':[0, 'FMC 1 software reset (active low)', 0x1],
'FMC1':[1, 'FMC 2 software reset (active low)', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}]
}]
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