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FMC ADC 100M 14b 4cha - Testing
Commit 08568437 authored by Matthieu Cattin's avatar Matthieu Cattin
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register maps: Add register map description string.

parent 2e52b071
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test/fmcadc100m14b4cha/python/carrier_csr.py
View file @ 08568437
......@@ -9,21 +9,21 @@
# Control and status registers of the SPEC board
CARRIER_CSR={
'CARRIER':[0x00, 'Carrier', {
'PCB_REV':[0, 'PCB revision', 0xF],
'TYPE':[16, 'Carrier type', 0xFFFF]}],
'BITSTREAM_TYPE':[0x04, 'Bitstream type', {
'BITSTREAM_TYPE':[0, 'Bitstream type', 0xFFFFFFFF]}],
'BITSTREAM_DATE':[0x08, 'Bitstream date', {
'BITSTREAM_DATE':[0, 'Bitstream date', 0xFFFFFFFF]}],
'STAT':[0x0C, 'Status', {
'FMC_PRES':[0, 'FMC presence (active low)', 0x1],
'P2L_PLL_LCK':[1, 'P2L PLL locked', 0x1],
'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
'DDR3_CAL_DONE':[3, 'DDR3 calibration done', 0x1]}],
'CTRL':[0x10, 'Control', {
'LED_GREEN':[0, 'Green LED', 0x1],
'LED_RED':[1, 'Red LED', 0x1],
'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1]}]
}
CARRIER_CSR=['Carrier control and status registers',{
'CARRIER':[0x00, 'Carrier', {
'PCB_REV':[0, 'PCB revision', 0xF],
'TYPE':[16, 'Carrier type', 0xFFFF]}],
'BITSTREAM_TYPE':[0x04, 'Bitstream type', {
'BITSTREAM_TYPE':[0, 'Bitstream type', 0xFFFFFFFF]}],
'BITSTREAM_DATE':[0x08, 'Bitstream date', {
'BITSTREAM_DATE':[0, 'Bitstream date', 0xFFFFFFFF]}],
'STAT':[0x0C, 'Status', {
'FMC_PRES':[0, 'FMC presence (active low)', 0x1],
'P2L_PLL_LCK':[1, 'P2L PLL locked', 0x1],
'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
'DDR3_CAL_DONE':[3, 'DDR3 calibration done', 0x1]}],
'CTRL':[0x10, 'Control', {
'LED_GREEN':[0, 'Green LED', 0x1],
'LED_RED':[1, 'Red LED', 0x1],
'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1]}]
}]
test/fmcadc100m14b4cha/python/irq_controller_regs.py
View file @ 08568437
......@@ -9,20 +9,20 @@
# IRQ controller core registers
IRQ_CONTROLLER_REGS={
'MULTI_IRQ':[0x00, 'Multiple interrupt', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'SRC':[0x04, 'Interrupt sources', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'EN_MASK':[0x08, 'Interrupt enable mask', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}]
}
IRQ_CONTROLLER_REGS=['IRQ controller registers', {
'MULTI_IRQ':[0x00, 'Multiple interrupt', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'SRC':[0x04, 'Interrupt sources', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'EN_MASK':[0x08, 'Interrupt enable mask', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}]
}]
test/fmcadc100m14b4cha/python/utc_core_regs.py
View file @ 08568437
......@@ -9,23 +9,23 @@
# UTC core registers
UTC_CORE_REGS={
'SECONDS':[0x00, 'UTC seconds', {}],
'COARSE':[0x04, 'UTC coarse time (8ns resolution)', {}],
'TRIG_TAG_META':[0x08, 'Trigger time-tag metadata', {}],
'TRIG_TAG_SECONDS':[0x0C, 'Trigger time-tag UTC seconds', {}],
'TRIG_TAG_COARSE':[0x10, 'Trigger time-tag UTC coarse time', {}],
'TRIG_TAG_FINE':[0x14, 'Trigger time-tag fine time', {}],
'ACQ_START_TAG_META':[0x18, 'Acquisition start time-tag metadata', {}],
'ACQ_START_TAG_SECONDS':[0x1C, 'Acquisition start time-tag UTC seconds', {}],
'ACQ_START_TAG_COARSE':[0x20, 'Acquisition start time-tag UTC coarse time', {}],
'ACQ_START_TAG_FINE':[0x24, 'Acquisition start time-tag fine time', {}],
'ACQ_STOP_TAG_META':[0x28, 'Acquisition stop time-tag metadata', {}],
'ACQ_STOP_TAG_SECONDS':[0x2C, 'Acquisition stop time-tag UTC seconds', {}],
'ACQ_STOP_TAG_COARSE':[0x30, 'Acquisition stop time-tag UTC coarse time', {}],
'ACQ_STOP_TAG_FINE':[0x34, 'Acquisition stop time-tag fine time', {}],
'ACQ_END_TAG_META':[0x38, 'Acquisition end time-tag metadata', {}],
'ACQ_END_TAG_SECONDS':[0x3C, 'Acquisition end time-tag UTC seconds', {}],
'ACQ_END_TAG_COARSE':[0x40, 'Acquisition end time-tag UTC coarse time', {}],
'ACQ_END_TAG_FINE':[0x44, 'Acquisition end time-tag fine time', {}]
}
UTC_CORE_REGS=['UTC core registers', {
'SECONDS':[0x00, 'UTC seconds', {}],
'COARSE':[0x04, 'UTC coarse time (8ns resolution)', {}],
'TRIG_TAG_META':[0x08, 'Trigger time-tag metadata', {}],
'TRIG_TAG_SECONDS':[0x0C, 'Trigger time-tag UTC seconds', {}],
'TRIG_TAG_COARSE':[0x10, 'Trigger time-tag UTC coarse time', {}],
'TRIG_TAG_FINE':[0x14, 'Trigger time-tag fine time', {}],
'ACQ_START_TAG_META':[0x18, 'Acquisition start time-tag metadata', {}],
'ACQ_START_TAG_SECONDS':[0x1C, 'Acquisition start time-tag UTC seconds', {}],
'ACQ_START_TAG_COARSE':[0x20, 'Acquisition start time-tag UTC coarse time', {}],
'ACQ_START_TAG_FINE':[0x24, 'Acquisition start time-tag fine time', {}],
'ACQ_STOP_TAG_META':[0x28, 'Acquisition stop time-tag metadata', {}],
'ACQ_STOP_TAG_SECONDS':[0x2C, 'Acquisition stop time-tag UTC seconds', {}],
'ACQ_STOP_TAG_COARSE':[0x30, 'Acquisition stop time-tag UTC coarse time', {}],
'ACQ_STOP_TAG_FINE':[0x34, 'Acquisition stop time-tag fine time', {}],
'ACQ_END_TAG_META':[0x38, 'Acquisition end time-tag metadata', {}],
'ACQ_END_TAG_SECONDS':[0x3C, 'Acquisition end time-tag UTC seconds', {}],
'ACQ_END_TAG_COARSE':[0x40, 'Acquisition end time-tag UTC coarse time', {}],
'ACQ_END_TAG_FINE':[0x44, 'Acquisition end time-tag fine time', {}]
}]
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