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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
239434ba
Commit
239434ba
authored
May 26, 2014
by
Matthieu Cattin
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struct: Update VME tests paths to fit new folder structure.
parent
adc00413
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Showing
10 changed files
with
81 additions
and
108 deletions
+81
-108
pts
pts
+1
-1
fmc_adc_svec.py
tests/fmc_adc_svec.py
+7
-0
svec_test00.py
tests/svec_test00.py
+7
-12
svec_test01.py
tests/svec_test01.py
+17
-17
svec_test12.py
tests/svec_test12.py
+7
-12
svec_test30.py
tests/svec_test30.py
+9
-14
svec_test34.py
tests/svec_test34.py
+7
-12
svec_test36.py
tests/svec_test36.py
+9
-14
svec_test37.py
tests/svec_test37.py
+9
-13
svec_test42.py
tests/svec_test42.py
+8
-13
No files found.
pts
@
f9d07331
Subproject commit
09ed4c4bb283b0dacd6ed36d016b85a26169b371
Subproject commit
f9d07331c1477487a9fae97284beb1fb4c14c4d3
tests/fmc_adc_svec.py
View file @
239434ba
...
...
@@ -9,10 +9,17 @@
# Import standard modules
import
sys
import
os
import
time
import
random
import
math
# Add common modules and libraries location to path
cdir
=
os
.
path
.
dirname
(
os
.
path
.
realpath
(
__file__
))
sys
.
path
.
append
(
os
.
path
.
join
(
cdir
,
'../pts/'
))
sys
.
path
.
append
(
os
.
path
.
join
(
cdir
,
'../pts/common/'
))
sys
.
path
.
append
(
os
.
path
.
join
(
cdir
,
'../../svec_pts/ubuntu/pts/pyts/'
))
# Import specific modules
from
sdb
import
*
from
csr
import
*
...
...
tests/svec_test00.py
View file @
239434ba
#!
./
python
#!
/usr/bin/env
python
# coding: utf8
# Copyright CERN, 2013
...
...
@@ -11,21 +11,16 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import specific modules
from
fmc_adc_svec
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
"""
test00: Load
firmware, verify firm
ware type and test mezzanine presence line.
test00: Load
gateware, verify gate
ware type and test mezzanine presence line.
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -33,7 +28,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
0
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
...
...
@@ -48,8 +43,8 @@ def main (default_directory='.'):
print
"Initialising device.
\n
"
bus
.
vv_init
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
time
.
sleep
(
2
)
...
...
tests/svec_test01.py
View file @
239434ba
...
...
@@ -11,19 +11,14 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
"""
svec_test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...)
...
...
@@ -35,7 +30,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
1
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
NB_CHANNELS
=
4
...
...
@@ -53,15 +48,15 @@ def main (default_directory='.'):
bus
=
VME_rr_compatible
(
LUN
)
print
"Initialising device.
\n
"
# Load FMC ADC
firm
ware
# Load FMC ADC
gate
ware
ask
=
'N'
while
((
ask
!=
"Y"
)
and
(
ask
!=
"N"
))
:
ask
=
raw_input
(
"Do you want to load the
firm
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
raw_input
(
"Do you want to load the
gate
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
ask
.
upper
()
print
" "
if
(
ask
==
"Y"
):
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
bus
.
vv_init
()
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
...
...
@@ -188,20 +183,25 @@ def main (default_directory='.'):
print
(
'The external trigger input is working fine.'
)
# DDR access
rd_size
=
8
# 32-bit words
wr_size
=
rd_size
/
2
print
(
'
\n
Test DDR access'
)
ddr_data_rd
=
fmc
[
i
]
.
get_data
(
0x0
,
16
,
raw
=
True
)
ddr_data_rd
=
fmc
[
i
]
.
get_data
(
0x0
,
rd_size
*
4
,
raw
=
True
)
ddr_data_wr
=
range
(
8
)
ddr_data_wr
=
range
(
wr_size
)
fmc
[
i
]
.
put_data
(
0x0
,
ddr_data_wr
)
ddr_data_wr
.
extend
([
0x0
]
*
8
)
ddr_data_wr
.
extend
([
0x0
]
*
wr_size
)
ddr_data_rdb
=
fmc
[
i
]
.
get_data
(
0x0
,
16
,
raw
=
True
)
ddr_data_rdb
=
fmc
[
i
]
.
get_data
(
0x0
,
rd_size
*
4
,
raw
=
True
)
ddr_data_exp
=
ddr_data_wr
[
0
:
8
]
+
ddr_data_rd
[
8
:
16
]
ddr_data_exp
=
ddr_data_wr
[
0
:
wr_size
]
+
ddr_data_rd
[
wr_size
:
rd_size
]
print
(
'addr: read: written: read back expected:'
)
for
j
in
range
(
len
(
ddr_data_rd
)):
print
(
'
%.3
d 0x
%.8
x 0x
%.8
x 0x
%.8
x 0x
%.8
x'
%
(
j
,
ddr_data_rd
[
j
],
ddr_data_wr
[
j
],
ddr_data_rdb
[
j
],
ddr_data_exp
[
j
]))
print
ddr_data_rdb
print
ddr_data_exp
if
ddr_data_rdb
!=
ddr_data_exp
:
error
[
i
]
=
'Error in ddr access'
continue
...
...
tests/svec_test12.py
View file @
239434ba
...
...
@@ -12,26 +12,21 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
"""
svec_test12: Takes an aqcuisition of all channels and print it to a file
Set UTC and read UTC time-tags
Note: Requires svec_test00.py to run first to load the
firm
ware!
Note: Requires svec_test00.py to run first to load the
gate
ware!
"""
...
...
@@ -55,7 +50,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
12
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
...
...
@@ -69,7 +64,7 @@ def main (default_directory='.'):
bus
.
vv_open
()
# Carrier object declaration (SVEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSvec
(
bus
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSvecOperationError
as
e
:
...
...
tests/svec_test30.py
View file @
239434ba
...
...
@@ -12,25 +12,20 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
"""
svec_test30: Test software reset.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -109,7 +104,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
30
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
...
...
@@ -128,14 +123,14 @@ def main (default_directory='.'):
print
"Initialising device.
\n
"
bus
.
vv_init
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
time
.
sleep
(
2
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSvec
(
bus
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSvecOperationError
as
e
:
...
...
tests/svec_test34.py
View file @
239434ba
...
...
@@ -11,19 +11,14 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
"""
test34: Test interrupts
...
...
@@ -36,7 +31,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
34
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
NB_CHANNELS
=
4
...
...
@@ -55,15 +50,15 @@ def main (default_directory='.'):
bus
=
VME_rr_compatible
(
LUN
)
print
"Initialising device.
\n
"
# Load FMC ADC
firm
ware
# Load FMC ADC
gate
ware
ask
=
''
while
((
ask
!=
"Y"
)
and
(
ask
!=
"N"
))
:
ask
=
raw_input
(
"Do you want to load the
firm
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
raw_input
(
"Do you want to load the
gate
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
ask
.
upper
()
print
" "
if
(
ask
==
"Y"
):
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
bus
.
vv_init
()
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
...
...
tests/svec_test36.py
View file @
239434ba
...
...
@@ -12,25 +12,20 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
"""
svec_test36: Test SDB records.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -39,7 +34,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
36
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
...
...
@@ -58,14 +53,14 @@ def main (default_directory='.'):
print
"Initialising device.
\n
"
bus
.
vv_init
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
time
.
sleep
(
2
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSvec
(
bus
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSvecOperationError
as
e
:
...
...
tests/svec_test37.py
View file @
239434ba
...
...
@@ -12,24 +12,20 @@ import sys
import
time
import
os
#
Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
#
Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
"""
svec_test37: Test trigger timetags (single and multi shot modes)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
NB_CHANNELS
=
4
...
...
@@ -106,7 +102,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
37
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
...
...
@@ -122,14 +118,14 @@ def main (default_directory='.'):
print
"Initialising device.
\n
"
bus
.
vv_init
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
time
.
sleep
(
2
)
# Carrier object declaration (SVEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSvec
(
bus
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSvecOperationError
as
e
:
...
...
tests/svec_test42.py
View file @
239434ba
...
...
@@ -11,20 +11,15 @@ import sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
from
numpy
import
*
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
"""
svec_test42: Tests sampling frequency counter
...
...
@@ -35,7 +30,7 @@ def main (default_directory='.'):
# Constants declaration
LUN
=
0
TEST_NB
=
42
FMC_ADC_BITSTREAM
=
'../../
../../../firm
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../../
gate
wares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
NB_CHANNELS
=
4
...
...
@@ -53,15 +48,15 @@ def main (default_directory='.'):
bus
=
VME_rr_compatible
(
LUN
)
print
"Initialising device.
\n
"
# Load FMC ADC
firm
ware
# Load FMC ADC
gate
ware
ask
=
''
while
((
ask
!=
"Y"
)
and
(
ask
!=
"N"
))
:
ask
=
raw_input
(
"Do you want to load the
firm
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
raw_input
(
"Do you want to load the
gate
ware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
ask
.
upper
()
print
" "
if
(
ask
==
"Y"
):
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
bus
.
vv_init
()
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
...
...
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