Commit 4e3a3b20 authored by Matthieu Cattin's avatar Matthieu Cattin

test44: comment out change of sampling clock.

For now, the clock is fixed at 100MHz, due to fpga pll constraints.
parent 85e7e58d
......@@ -266,7 +266,6 @@ def main (default_directory='.'):
time.sleep(3)
fs_clk = fmc.get_samp_freq()
print("Sampling frequency: %d Hz"%fs_clk)
"""
print("\Reduce sampling frequency")
fmc.si570.wr_reg(0x89,(1<<4)) # freeze DCO
......@@ -286,6 +285,8 @@ def main (default_directory='.'):
fmc.si570.recall_nvm()
fmc.print_si570_config()
"""
time.sleep(3)
fs_clk = fmc.get_samp_freq()
print("Sampling frequency: %d Hz"%fs_clk)
......
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