Commit c0fe7597 authored by Matthieu Cattin's avatar Matthieu Cattin

Add EEPROM write/readback in test02, increase tolerance in test07, add recovery…

Add EEPROM write/readback in test02, increase tolerance in test07, add recovery mechanism in test09.
parent 7b15a673
#!/usr/bin/python
import sys
import rr
import time
import i2c
class C24AA64:
def __init__(self, i2c, i2c_addr):
self.i2c = i2c
self.i2c_addr = i2c_addr
def wr_data(self, mem_addr, data):
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
#print('24AA64:write: data lenght=%d')%(len(data))
for i in range(len(data)-1):
#print('24AA64:write: i=%d')%(i)
self.i2c.write(data[i],False)
i += 1
#print('24AA64:write:last i=%d')%(i)
self.i2c.write(data[i],True)
return 0;
def rd_data(self, mem_addr, size):
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
self.i2c.start(self.i2c_addr, False)
data = []
#print('24AA64:read: data lenght=%d')%(size)
for i in range(size-1):
data.append(self.i2c.read(False))
#print('24AA64:read: i=%d')%(i)
i += 1
#print('24AA64:read:last i=%d')%(i)
data.append(self.i2c.read(True))
return data;
......@@ -14,6 +14,7 @@ import onewire
import ds18b20
#import mcp9801
import si57x
import eeprom_24aa64
class CFmcAdc100Ms:
......@@ -127,6 +128,7 @@ class CFmcAdc100Ms:
def __init__(self, bus):
self.bus = bus
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.bus, self.FMC_SYS_I2C_ADDR, 249)
self.eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
self.fmc_spi = spi.COpenCoresSPI(self.bus, self.FMC_SPI_ADDR, self.FMC_SPI_DIV)
self.adc_cfg = ltc217x.CLTC217x(self.fmc_spi, self.FMC_SPI_SS['ADC'])
self.fmc_i2c = i2c.COpenCoresI2C(self.bus, self.FMC_I2C_ADDR, 249)
......@@ -206,6 +208,14 @@ class CFmcAdc100Ms:
print '\nScan system I2C bus'
return self.fmc_sys_i2c.scan()
# write to EEPROM on system i2c bus
def sys_i2c_eeprom_write(self, addr, data):
return self.eeprom_24aa64.wr_data(addr, data)
# read from EEPROM on system i2c bus
def sys_i2c_eeprom_read(self, addr, size):
return self.eeprom_24aa64.rd_data(addr, size)
# Set input range
def set_input_range(self, channel, range):
addr = self.channel_addr(channel,self.R_CH1_SSR)
......
......@@ -57,9 +57,12 @@ class COpenCoresI2C:
pass
def start(self, addr, write_mode):
#print('i2c:start: addr=%.2X')%addr
addr = addr << 1
#print('i2c:start: addr=%.2X')%addr
if(write_mode == False):
addr = addr | 1
#print('i2c:start: addr=%.2X')%addr
self.wr_reg(self.R_TXR, addr)
#print("R_TXR: %.2X") % self.rd_reg(self.R_TXR)
self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR)
......
......@@ -60,9 +60,9 @@ def main (default_directory='.'):
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('bitstream type:%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsFatal ("Firmware not properly loaded.")
raise PtsCritical ("Firmware not properly loaded.")
if(bitstream_type != 0x1):
raise PtsFatal ("Wrong bitstream type.")
raise PtsCritical ("Wrong bitstream type.")
# Dump carrier CSR to log
print("PCB version : %d") % (PCB_VER_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))
......
......@@ -56,6 +56,22 @@ def main (default_directory='.'):
if(EEPROM_ADDR != periph_addr[0]):
raise PtsError('Wrong device mounted on system management I2C bus, address is:0x%.2X expected:0x%.2X'%(periph_addr[0],EEPROM_ADDR))
# Write, read back and compare
addr = 0x20
wr_data = [0x55, 0xAA, 0x00, 0xFF]
rd_data = []
print('Write data at EEPROM address:0x%.2X')%addr
print wr_data
fmc.sys_i2c_eeprom_write(addr, wr_data)
time.sleep(0.1)
print('Read back data from EEPROM address:0x%.2X')%addr
rd_data = fmc.sys_i2c_eeprom_read(addr, len(wr_data))
print rd_data
if(rd_data != wr_data):
raise PtsError('Cannot access EEPROM at address:0x%.2X'%(EEPROM_ADDR))
else:
print('Data comparison OK.')
if __name__ == '__main__' :
main()
......@@ -26,7 +26,7 @@ OFFSET_NEG = 0x0000
ADC_POS = 0x0000
ADC_MID = 0x8000
ADC_NEG = 0xFFFC
ADC_TOL = 0x100
ADC_TOL = 0x150
def main (default_directory='.'):
"""
......@@ -73,7 +73,7 @@ def main (default_directory='.'):
# Read channels current data register
for i in range(1,NB_CHANNELS+1):
adc_value = fmc.get_current_adc_value(i)
print('ADC channel %d value:0x%.4X') % (i, adc_value)
print('ADC channel %d value:0x%.4X tolerance:0x%.4X') % (i, adc_value, ADC_TOL)
if((ADC_MID-ADC_TOL > adc_value) | (ADC_MID+ADC_TOL < adc_value)):
raise PtsError('Channel %d offset circuit is malfunctioning'%i)
......
......@@ -10,8 +10,8 @@ import sys
import rr
import time
import os
#from numpy import *
#from pylab import *
from numpy import *
from pylab import *
from ptsexcept import *
......@@ -36,6 +36,8 @@ NB_CHANNELS = 4
AWG_SET_SLEEP = 1
SSR_SET_SLEEP = 0.05
ACQ_TIMEOUT = 10
PRE_TRIG_SAMPLES = 1000
POST_TRIG_SAMPLES = 1000
NB_SHOTS = 1
......@@ -96,17 +98,38 @@ def load_firmware(default_directory):
time.sleep(2);
def open_all_channels(fmc):
for i in range(1,NB_CHANNELS+1):
fmc.set_input_range(i, 'OPEN')
time.sleep(SSR_SET_SLEEP)
def fmc_adc_init(spec, fmc):
print('Initialise FMC board.')
fmc.__init__(spec)
# Reset offset DACs
fmc.dc_offset_reset()
# Make sure all switches are OFF
open_all_channels(fmc)
# Set trigger
# hw trig, rising edge, external, sw disable, no delay
fmc.set_trig_config(1, 0, 1, 1, 0, 0, 0)
# Set acquisition
fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
fmc.set_shots(NB_SHOTS)
# Print configuration
fmc.print_adc_core_config()
def set_awg_freq(gen, sine, freq):
sine.frequency = freq
gen.play(sine)
print('Sine frequency:%3.3fMHz')%(sine.frequency/1E6)
time.sleep(AWG_SET_SLEEP)
def acquisition(gnum, pages, fmc, channel_nb, channel_data):
# Start acquisition
fmc.stop_acq()
......@@ -114,9 +137,13 @@ def acquisition(gnum, pages, fmc, channel_nb, channel_data):
fmc.start_acq()
# Wait end of acquisition
timeout = 0
while('IDLE' != fmc.get_acq_fsm_state()):
#print fmc.get_acq_fsm_state()
time.sleep(.1)
timeout += 1
if(ACQ_TIMEOUT < timeout):
raise PtsError('Acquisition timeout. Check that the AWG is switched ON and properly connected.')
# Retrieve data trough DMA
page1_data_before_dma = gnum.get_memory_page(1)
......@@ -124,12 +151,10 @@ def acquisition(gnum, pages, fmc, channel_nb, channel_data):
gnum.start_dma()
gnum.wait_irq()
page1_data = gnum.get_memory_page(1)
if(page1_data_before_dma == page1_data):
print('page1 before DMA:')
print page1_data_before_dma[0:20]
print('page1 after DMA:')
print page1_data[0:20]
#raise PtsError('Acquisition or DMA error')
page_zeros = [0] * len(page1_data)
if((page1_data_before_dma == page1_data) or (page_zeros == page1_data)):
print('#################### Acquisition or DMA error.')
#raise PtsWarning('Acquisition or DMA error.')
return -1
for i in range(len(page1_data)):
channel_data.append(page1_data[i] & 0xFFFF)
......@@ -161,6 +186,9 @@ def main (default_directory='.'):
gen = Agilent33250A(device=USB_DEVICE, bauds=RS232_BAUD)
sine = SineWaveform()
# Initialise fmc adc
fmc_adc_init(spec, fmc)
# Set sine params
sine.frequency = 1E6
sine.amplitude = 0.25
......@@ -172,26 +200,14 @@ def main (default_directory='.'):
gen.play(sine)
gen.output = True
# Reset offset DACs
fmc.dc_offset_reset()
# Make sure all switches are OFF
open_all_channels(fmc)
# Get physical addresses of the pages for DMA transfer
pages = gnum.get_physical_addr()
# Set trigger
# hw trig, rising edge, external, sw disable, no delay
fmc.set_trig_config(1, 0, 1, 1, 0, 0, 0)
# Set acquisition
fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
fmc.set_shots(NB_SHOTS)
# Test frequency response of all channels
ch_diff = []
for j in range(len(points)):
j = 0
while(j < len(points)):
#print('begin loop j=%d')%(j)
set_awg_freq(gen, sine, points[j][0])
for i in range(1,NB_CHANNELS+1):
fmc.set_input_range(i, '1V')
......@@ -200,7 +216,8 @@ def main (default_directory='.'):
error = acquisition(gnum, pages, fmc, i, channel_data)
if(error != 0):
load_firmware(default_directory)
j -= 1
fmc_adc_init(spec, fmc)
#time.sleep(2)
break
diff = max(channel_data)-min(channel_data)
print('CH%d diff:%d')%(i, diff)
......@@ -210,6 +227,10 @@ def main (default_directory='.'):
print('Channel %d frequency response is out of range at freq:%2.3fMHz')%(i, points[j][0]/1E6)
print('Current amplitude:%d, expected:%d +/-%d')%(diff, points[j][1], points[j][2])
raise PtsError('Channel %d frequency response is out of range at freq:%2.3fMHz'%(i, points[j][0]/1E6))
if(error == 0):
j += 1
#print('j++')
#print('end loop j=%d')%(j)
# The following code is to show a graph of the test results
# !! Don't forget to import numpy and pylab !!
......
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