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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
d10fc5c9
Commit
d10fc5c9
authored
Nov 28, 2011
by
Matthieu Cattin
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Test programs modified after memory map modification for ADC core.
parent
bb9dffd9
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Showing
7 changed files
with
79 additions
and
54 deletions
+79
-54
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+51
-38
test00.py
test/fmcadc100m14b4cha/python/test00.py
+1
-1
test09.py
test/fmcadc100m14b4cha/python/test09.py
+6
-1
test11.py
test/fmcadc100m14b4cha/python/test11.py
+5
-0
test12.py
test/fmcadc100m14b4cha/python/test12.py
+4
-5
test14.py
test/fmcadc100m14b4cha/python/test14.py
+11
-8
test15.py
test/fmcadc100m14b4cha/python/test15.py
+1
-1
No files found.
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
d10fc5c9
...
...
@@ -39,23 +39,26 @@ class CFmcAdc100Ms:
0x10
:
'Software trigger register'
,
0x14
:
'Number of shots register'
,
0x18
:
'Trigger position register'
,
0x1C
:
'Gain calibration register'
,
0x20
:
'Offset calibration register'
,
0x24
:
'Reserved register'
,
0x28
:
'Reserved register'
,
0x2C
:
'Reserved register'
,
0x30
:
'Decimation factor register'
,
0x34
:
'Pre-trigger samples register'
,
0x38
:
'Post-trigger samples register'
,
0x3C
:
'Samples counter register'
,
0x40
:
'CH1 control register'
,
0x44
:
'CH1 current value register'
,
0x48
:
'CH2 control register'
,
0x4C
:
'CH2 current value register'
,
0x50
:
'CH3 control register'
,
0x54
:
'CH3 current value register'
,
0x58
:
'CH4 control register'
,
0x5C
:
'CH4 current value register'
,}
0x1C
:
'Decimation factor register'
,
0x20
:
'Pre-trigger samples register'
,
0x24
:
'Post-trigger samples register'
,
0x28
:
'Samples counter register'
,
0x2C
:
'CH1 control register'
,
0x30
:
'CH1 current value register'
,
0x34
:
'CH1 gain calibration register'
,
0x38
:
'CH1 offset calibration register'
,
0x3C
:
'CH2 control register'
,
0x40
:
'CH2 current value register'
,
0x44
:
'CH2 gain calibration register'
,
0x48
:
'CH2 offset calibration register'
,
0x4C
:
'CH3 control register'
,
0x50
:
'CH3 current value register'
,
0x54
:
'CH3 gain calibration register'
,
0x58
:
'CH3 offset calibration register'
,
0x5C
:
'CH4 control register'
,
0x60
:
'CH4 current value register'
,
0x64
:
'CH4 gain calibration register'
,
0x68
:
'CH4 offset calibration register'
,}
FMC_CSR_ADDR
=
0x90000
R_CTL
=
0x00
R_STA
=
0x04
...
...
@@ -64,23 +67,26 @@ class CFmcAdc100Ms:
R_SW_TRIG
=
0x10
R_SHOTS
=
0x14
R_TRIG_POS
=
0x18
R_GAIN_CAL
=
0x1C
R_OFFSET_CAL
=
0x20
R_RESERVED_0
=
0x24
R_RESERVED_1
=
0x28
R_RESERVED_2
=
0x2C
R_SRATE
=
0x30
R_PRE_SAMPLES
=
0x34
R_POST_SAMPLES
=
0x38
R_SAMP_CNT
=
0x3C
R_CH1_SSR
=
0x40
R_CH1_VALUE
=
0x44
R_CH2_SSR
=
0x48
R_CH2_VALUE
=
0x4C
R_CH3_SSR
=
0x50
R_CH3_VALUE
=
0x54
R_CH4_SSR
=
0x58
R_CH4_VALUE
=
0x5C
R_SRATE
=
0x1C
R_PRE_SAMPLES
=
0x20
R_POST_SAMPLES
=
0x24
R_SAMP_CNT
=
0x28
R_CH1_SSR
=
0x2C
R_CH1_VALUE
=
0x30
R_CH1_GAIN
=
0x34
R_CH1_OFFSET
=
0x38
R_CH2_SSR
=
0x3C
R_CH2_VALUE
=
0x40
R_CH2_GAIN
=
0x44
R_CH2_OFFSET
=
0x48
R_CH3_SSR
=
0x4C
R_CH3_VALUE
=
0x50
R_CH3_GAIN
=
0x54
R_CH1_OFFSET
=
0x58
R_CH4_SSR
=
0x5C
R_CH4_VALUE
=
0x60
R_CH4_GAIN
=
0x64
R_CH4_OFFSET
=
0x68
CTL_FSM_CMD
=
0
CTL_CLK_EN
=
2
...
...
@@ -121,12 +127,13 @@ class CFmcAdc100Ms:
if
(
channel
<
1
or
channel
>
4
):
raise
Exception
(
'Channel number not in range (1 to 4).'
)
else
:
addr
=
(
reg
+
(
8
*
(
channel
-
1
)))
addr
=
(
reg
+
(
0x10
*
(
channel
-
1
)))
#print("Channel %d address: %.2X") % (channel, addr)
return
addr
def
__init__
(
self
,
bus
):
self
.
bus
=
bus
# Objects declaration
self
.
fmc_sys_i2c
=
i2c
.
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_SYS_I2C_ADDR
,
249
)
self
.
eeprom_24aa64
=
eeprom_24aa64
.
C24AA64
(
self
.
fmc_sys_i2c
,
self
.
EEPROM_ADDR
)
self
.
fmc_spi
=
spi
.
COpenCoresSPI
(
self
.
bus
,
self
.
FMC_SPI_ADDR
,
self
.
FMC_SPI_DIV
)
...
...
@@ -134,14 +141,20 @@ class CFmcAdc100Ms:
self
.
fmc_i2c
=
i2c
.
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_I2C_ADDR
,
249
)
self
.
fmc_onewire
=
onewire
.
COpenCoresOneWire
(
self
.
bus
,
self
.
FMC_ONEWIRE_ADDR
,
624
,
124
)
self
.
ds18b20
=
ds18b20
.
CDS18B20
(
self
.
fmc_onewire
,
0
)
#self.mcp9801 = mcp9801.CMCP9801(self.fmc_i2c, self.MCP9801_ADDR)
self
.
si570
=
si57x
.
CSi57x
(
self
.
fmc_i2c
,
self
.
SI570_ADDR
)
self
.
fmc_adc_csr
=
csr
.
CCSR
(
self
.
bus
,
self
.
FMC_CSR_ADDR
)
self
.
dac_ch1
=
max5442
.
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC1'
])
self
.
dac_ch2
=
max5442
.
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC2'
])
self
.
dac_ch3
=
max5442
.
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC3'
])
self
.
dac_ch4
=
max5442
.
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC4'
])
# Set channels gaim to 1
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CH1_GAIN
,
0x8000
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CH2_GAIN
,
0x8000
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CH3_GAIN
,
0x8000
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CH4_GAIN
,
0x8000
)
# Enable mezzanine clock and offset DACs
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
((
1
<<
self
.
CTL_CLK_EN
)
|
(
1
<<
self
.
CTL_OFFSET_DAC_CLR_N
)))
# Disable ADC test pattern
self
.
adc_cfg
.
dis_testpat
()
#def __del__(self):
...
...
@@ -492,8 +505,8 @@ class CFmcAdc100Ms:
def
print_adc_core_config
(
self
):
print
(
"
\n
ADC core configuration/status"
)
self
.
fmc_adc_csr
.
rd_reg
(
0x04
)
# Workaround for first read at 0x00 bug
for
i
in
range
(
0
,
0x6
0
,
4
):
print
(
"
%3
0
s:
%.8
X"
)
%
(
self
.
FMC_CSR
[
i
]
,
self
.
fmc_adc_csr
.
rd_reg
(
i
))
for
i
in
range
(
0
,
0x6
C
,
4
):
print
(
"
%3
1
s: 0x
%.8
X (
%
d)"
)
%
(
self
.
FMC_CSR
[
i
],
self
.
fmc_adc_csr
.
rd_reg
(
i
)
,
self
.
fmc_adc_csr
.
rd_reg
(
i
))
# Print Si570 config
def
print_si570_config
(
self
):
...
...
test/fmcadc100m14b4cha/python/test00.py
View file @
d10fc5c9
...
...
@@ -43,7 +43,7 @@ CTRL_DAC_CLR_N = (1<<2)
def
main
(
default_directory
=
'.'
):
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha.bin'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha
_test
.bin'
;
firmware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_firmware
)
...
...
test/fmcadc100m14b4cha/python/test09.py
View file @
d10fc5c9
...
...
@@ -16,6 +16,7 @@ from pylab import *
from
ptsexcept
import
*
import
gn4124
import
spec_fmc_adc
import
fmc_adc
from
PAGE.Agilent33250A
import
*
from
PAGE.SineWaveform
import
*
...
...
@@ -91,7 +92,7 @@ points = [[1E6, 36300, 1000],
def
load_firmware
(
default_directory
):
print
(
'Load firmware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha.bin'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha
_test
.bin'
;
firmware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_firmware
)
...
...
@@ -205,10 +206,14 @@ def main (default_directory='.'):
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
gnum
=
gn4124
.
CGN4124
(
spec
,
GN4124_CSR
)
spec_fmc
=
spec_fmc_adc
.
CSpecFmcAdc100Ms
(
spec
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
gen
=
Agilent33250A
(
device
=
USB_DEVICE
,
bauds
=
RS232_BAUD
)
sine
=
SineWaveform
()
# Enable "DMA finished" IRQ
spec_fmc
.
set_irq_en_mask
(
0x1
)
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
...
...
test/fmcadc100m14b4cha/python/test11.py
View file @
d10fc5c9
...
...
@@ -16,6 +16,7 @@ from pylab import *
from
ptsexcept
import
*
import
gn4124
import
spec_fmc_adc
import
fmc_adc
from
PAGE.Agilent33250A
import
*
from
PAGE.SineWaveform
import
*
...
...
@@ -164,10 +165,14 @@ def main (default_directory='.'):
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
gnum
=
gn4124
.
CGN4124
(
spec
,
GN4124_CSR
)
spec_fmc
=
spec_fmc_adc
.
CSpecFmcAdc100Ms
(
spec
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
gen
=
Agilent33250A
(
device
=
USB_DEVICE
,
bauds
=
RS232_BAUD
)
sine
=
SineWaveform
()
# Enables DMA interrupts
print
(
'Set IRQ enable mask:
%.4
X'
)
%
spec_fmc
.
set_irq_en_mask
(
0x3
)
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
...
...
test/fmcadc100m14b4cha/python/test12.py
View file @
d10fc5c9
...
...
@@ -41,8 +41,8 @@ ACQ_TIMEOUT = 10
MAX_FIRMWARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
256
POST_TRIG_SAMPLES
=
256
PRE_TRIG_SAMPLES
=
100
POST_TRIG_SAMPLES
=
1000
NB_SHOTS
=
1
DMA_LENGTH
=
4096
# DMA length in bytes
...
...
@@ -74,9 +74,8 @@ def fmc_adc_init(spec, fmc):
fmc
.
dc_offset_reset
()
# Make sure all switches are OFF
open_all_channels
(
fmc
)
# Set trigger
# hw trig, rising edge, external, sw disable, no delay
fmc
.
set_trig_config
(
1
,
0
,
1
,
1
,
0
,
0
,
0
)
# Set trigger (external trigger on rising edge)
fmc
.
set_ext_trig
(
0
)
# Set acquisition
fmc
.
set_pre_trig_samples
(
PRE_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
...
...
test/fmcadc100m14b4cha/python/test14.py
View file @
d10fc5c9
...
...
@@ -75,8 +75,7 @@ def fmc_adc_init(spec, fmc):
# Make sure all switches are OFF
open_all_channels
(
fmc
)
# Set trigger
# hw trig, rising edge, external, sw disable, no delay
fmc
.
set_trig_config
(
1
,
0
,
1
,
1
,
0
,
0
,
0
)
fmc
.
set_soft_trig
()
# Set acquisition
fmc
.
set_pre_trig_samples
(
PRE_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
...
...
@@ -90,6 +89,10 @@ def acquisition(gnum, pages, fmc, channels_data, check_same, spec_fmc):
# Start acquisition
fmc
.
start_acq
()
# Wait end of acquisition
for
i
in
range
(
NB_SHOTS
):
time
.
sleep
(
0.1
)
fmc
.
sw_trig
()
print
(
'Software trigger nb:
%
d'
)
%
i
timeout
=
0
while
(
'IDLE'
!=
fmc
.
get_acq_fsm_state
()):
#print fmc.get_acq_fsm_state()
...
...
@@ -180,10 +183,10 @@ def main (default_directory='.'):
print
(
'Sine frequency:
%3.3
fMHz amplitude:
%2.3
fVp offset:
%2.3
fV'
)
%
(
sine
.
frequency
/
1E6
,
sine
.
amplitude
,
sine
.
dc
)
# Set AWG
#
gen.connect()
#
gen.play(sine)
#
gen.output = True
#
time.sleep(AWG_SET_SLEEP)
gen
.
connect
()
gen
.
play
(
sine
)
gen
.
output
=
True
time
.
sleep
(
AWG_SET_SLEEP
)
# Connects channel 4 to AWG
fmc
.
set_input_range
(
4
,
'1V'
)
...
...
@@ -247,8 +250,8 @@ def main (default_directory='.'):
open_all_channels
(
fmc
)
# Switch AWG OFF
#
gen.output = False
#
gen.close()
gen
.
output
=
False
gen
.
close
()
# Check if an error occured during frequency response test
if
(
error
!=
0
):
...
...
test/fmcadc100m14b4cha/python/test15.py
View file @
d10fc5c9
...
...
@@ -186,7 +186,7 @@ def main (default_directory='.'):
# Connects channel 4 to AWG
fmc
.
set_input_range
(
4
,
'10V'
)
fmc
.
set_input_range
(
3
,
'10V'
)
#
fmc.set_input_range(3, '10V')
time
.
sleep
(
SSR_SET_SLEEP
)
# Use test data instead of data from ADC
...
...
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