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FMC ADC 100M 14b 4cha - Testing
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Projects
FMC ADC 100M 14b 4cha - Testing
Commits
e6c22156
Commit
e6c22156
authored
May 21, 2014
by
Matthieu Cattin
Browse files
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struct: Rename firmware in gateware.
parent
b128b8ed
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Showing
46 changed files
with
262 additions
and
262 deletions
+262
-262
README
tests/README
+1
-1
fmc_adc_demo.py
tests/fmc_adc_demo.py
+8
-8
test00.py
tests/test00.py
+6
-6
test01.py
tests/test01.py
+1
-1
test02.py
tests/test02.py
+2
-2
test03.py
tests/test03.py
+2
-2
test04.py
tests/test04.py
+2
-2
test05.py
tests/test05.py
+2
-2
test06.py
tests/test06.py
+2
-2
test07.py
tests/test07.py
+2
-2
test08.py
tests/test08.py
+2
-2
test09.py
tests/test09.py
+2
-2
test10.py
tests/test10.py
+1
-1
test11.py
tests/test11.py
+18
-18
test12.py
tests/test12.py
+7
-7
test13.py
tests/test13.py
+10
-10
test14.py
tests/test14.py
+19
-19
test15.py
tests/test15.py
+20
-20
test16.py
tests/test16.py
+14
-14
test17.py
tests/test17.py
+8
-8
test19.py
tests/test19.py
+3
-3
test19_2.py
tests/test19_2.py
+12
-12
test19_eeprom.py
tests/test19_eeprom.py
+1
-1
test20.py
tests/test20.py
+4
-4
test22.py
tests/test22.py
+6
-6
test23.py
tests/test23.py
+1
-1
test25.py
tests/test25.py
+4
-4
test26.py
tests/test26.py
+2
-2
test27.py
tests/test27.py
+6
-6
test28.py
tests/test28.py
+7
-7
test29.py
tests/test29.py
+1
-1
test30.py
tests/test30.py
+7
-7
test31.py
tests/test31.py
+1
-1
test32.py
tests/test32.py
+6
-6
test33.py
tests/test33.py
+2
-2
test34.py
tests/test34.py
+2
-2
test35.py
tests/test35.py
+5
-5
test36.py
tests/test36.py
+6
-6
test37.py
tests/test37.py
+7
-7
test38.py
tests/test38.py
+7
-7
test39.py
tests/test39.py
+6
-6
test40.py
tests/test40.py
+6
-6
test41.py
tests/test41.py
+6
-6
test42.py
tests/test42.py
+6
-6
test43.py
tests/test43.py
+6
-6
test_loader_lib.py
tests/test_loader_lib.py
+13
-13
No files found.
tests/README
View file @
e6c22156
...
...
@@ -11,7 +11,7 @@ Website: http://www.ohwr.org/projects/pts
This batch of tests the fonctionnality of the FmcAdc100M14b4cha:
- test00: Loads
firm
ware and test mezzanine presence
- test00: Loads
gate
ware and test mezzanine presence
- test01: 1-wire: read serial unique ID and store
- test02: I2C EEPROM: write, read back and compare
- test03: LEDs: Switch ON and ask operator
...
...
tests/fmc_adc_demo.py
View file @
e6c22156
...
...
@@ -45,7 +45,7 @@ from PAGE.SineWaveform import *
# Constants declaration
NB_POINTS
=
1000
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
ADC_FS
=
10.0
USB_DEVICE
=
"/dev/ttyUSB0"
...
...
@@ -215,15 +215,15 @@ if __name__ == "__main__":
m
.
show
()
m
.
setWindowTitle
(
"Fmc Adc 100Ms/s Demo"
)
# Load
firm
ware to FPGA
# Load
gate
ware to FPGA
default_directory
=
'.'
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
#path_
firmware = '../firm
wares/spec_fmcadc100m14b4cha_test.bin';
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
#path_
gateware = '../gate
wares/spec_fmcadc100m14b4cha_test.bin';
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
# Objects declaration
...
...
tests/test00.py
View file @
e6c22156
...
...
@@ -26,7 +26,7 @@ from fmc_adc_spec import *
"""
test00: Load
firmware, verify firm
ware type and test mezzanine presence line.
test00: Load
gateware, verify gate
ware type and test mezzanine presence line.
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -34,7 +34,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
0
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -53,13 +53,13 @@ def main (default_directory='.'):
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
try
:
...
...
tests/test01.py
View file @
e6c22156
...
...
@@ -29,7 +29,7 @@ from fmc_adc import *
"""
test01: Test 1-wire thermometer and read the unique ID.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
tests/test02.py
View file @
e6c22156
...
...
@@ -29,7 +29,7 @@ from fmc_adc import *
"""
test02: Test EEPROM access
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
pattern_compare
(
fmc
,
pattern
):
...
...
@@ -71,7 +71,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test03.py
View file @
e6c22156
...
...
@@ -29,7 +29,7 @@ from fmc_adc import *
"""
test03: Test mezzanine front-panel LEDs
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -48,7 +48,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test04.py
View file @
e6c22156
...
...
@@ -28,7 +28,7 @@ from fmc_adc import *
"""
test04: Test Si570 programmable oscillator
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -52,7 +52,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test05.py
View file @
e6c22156
...
...
@@ -28,7 +28,7 @@ from fmc_adc import *
"""
test05: Test LTC2174 ADC
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -49,7 +49,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test06.py
View file @
e6c22156
...
...
@@ -32,7 +32,7 @@ from PAGE.SineWaveform import *
"""
test06: Test trigger input
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -59,7 +59,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test07.py
View file @
e6c22156
...
...
@@ -29,7 +29,7 @@ from numpy import *
"""
test07: Test offset DACs
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
NB_CHANNELS
=
4
...
...
@@ -128,7 +128,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test08.py
View file @
e6c22156
...
...
@@ -34,7 +34,7 @@ from PAGE.SineWaveform import *
"""
test08: Test analogue front-end switches
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -189,7 +189,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test09.py
View file @
e6c22156
...
...
@@ -36,7 +36,7 @@ from PAGE.SineWaveform import *
test09: Test analogue front-end frequency response,
with limits check
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
NB_CHANNELS
=
4
...
...
@@ -194,7 +194,7 @@ def main (default_directory='.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test10.py
View file @
e6c22156
...
...
@@ -20,7 +20,7 @@ from pylab import *
"""
test10: Plot frequency response summary data from test09_freq_resp.txt file
Note: Requires test00.py to run first to load the
firm
ware and
Note: Requires test00.py to run first to load the
gate
ware and
test09.py to generate the file.
"""
...
...
tests/test11.py
View file @
e6c22156
...
...
@@ -25,7 +25,7 @@ from PAGE.SineWaveform import *
"""
test11: Test acquisition chain
Note: If not used with Chipscope, requires test00.py to run first to load the
firm
ware!
Note: If not used with Chipscope, requires test00.py to run first to load the
gate
ware!
"""
GN4124_CSR
=
0x0
...
...
@@ -39,7 +39,7 @@ SSR_SET_SLEEP = 0.05
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
1000
POST_TRIG_SAMPLES
=
1000
...
...
@@ -48,15 +48,15 @@ NB_SHOTS = 1
DMA_LENGTH
=
4096
# DMA length in bytes
def
load_
firm
ware
(
default_directory
):
print
(
'Load
firm
ware to FPGA'
)
def
load_
gate
ware
(
default_directory
):
print
(
'Load
gate
ware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
@@ -150,14 +150,14 @@ def show_result_graph(points, ch_diff):
def
main
(
default_directory
=
'.'
):
"""
# Load
firm
ware to FPGA
# Load
gate
ware to FPGA
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_
firmware = '../firm
wares/spec_fmcadc100m14b4cha.bin';
path_
gateware = '../gate
wares/spec_fmcadc100m14b4cha.bin';
firm
ware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_
firm
ware)
print
firm
ware_loader + ' ' + bitstream
os.system(
firm
ware_loader + ' ' + bitstream )
gate
ware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_
gate
ware)
print
gate
ware_loader + ' ' + bitstream
os.system(
gate
ware_loader + ' ' + bitstream )
time.sleep(2);
"""
...
...
@@ -204,11 +204,11 @@ def main (default_directory='.'):
if
(
retry
!=
0
):
retry_cnt
+=
1
print
(
'RETRY:
%
d'
)
%
(
retry_cnt
)
if
(
MAX_
FIRM
WARE_RELOAD
<
retry_cnt
):
print
(
'Maximium of
%
d retry exceeded (channel:
%
d, freq:
%2.3
fMHz)'
)
%
(
MAX_
FIRM
WARE_RELOAD
,
i
,
points
[
j
][
0
]
/
1E6
)
if
(
MAX_
GATE
WARE_RELOAD
<
retry_cnt
):
print
(
'Maximium of
%
d retry exceeded (channel:
%
d, freq:
%2.3
fMHz)'
)
%
(
MAX_
GATE
WARE_RELOAD
,
i
,
points
[
j
][
0
]
/
1E6
)
error
+=
1
break
#load_
firm
ware(default_directory)
#load_
gate
ware(default_directory)
#fmc_adc_init(spec, fmc)
#time.sleep(2)
break
...
...
tests/test12.py
View file @
e6c22156
...
...
@@ -36,7 +36,7 @@ from PAGE.SineWaveform import *
test12: Takes an acquisition of each channels separately and print it to a file and on the screen
Set UTC and read UTC time-tags
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -143,7 +143,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
12
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -164,16 +164,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test13.py
View file @
e6c22156
...
...
@@ -21,28 +21,28 @@ import spec_fmc_adc
"""
test13: Test 1-wire thermometer and read the unique ID of the SPEC board.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
FAMILY_CODE
=
0x28
def
load_
firm
ware
(
default_directory
):
print
(
'Load
firm
ware to FPGA'
)
def
load_
gate
ware
(
default_directory
):
print
(
'Load
gate
ware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
def
main
(
default_directory
=
'.'
):
# Load
firm
ware
load_
firm
ware
(
default_directory
)
# Load
gate
ware
load_
gate
ware
(
default_directory
)
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
...
...
tests/test14.py
View file @
e6c22156
...
...
@@ -25,7 +25,7 @@ from PAGE.SineWaveform import *
"""
test14: pre-trigger ansd post-trigger counter test
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
GN4124_CSR
=
0x0
...
...
@@ -39,7 +39,7 @@ SSR_SET_SLEEP = 0.05
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
50
POST_TRIG_SAMPLES
=
50
...
...
@@ -48,15 +48,15 @@ NB_SHOTS = 3
DMA_LENGTH
=
4096
# DMA length in bytes
def
load_
firm
ware
(
default_directory
):
print
(
'Load
firm
ware to FPGA'
)
def
load_
gate
ware
(
default_directory
):
print
(
'Load
gate
ware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
@@ -134,19 +134,19 @@ def acquisition(gnum, pages, fmc, channels_data, check_same, spec_fmc):
def
main
(
default_directory
=
'.'
):
load_
firmware
=
raw_input
(
'Do you want to load the firm
ware? [y,n]'
)
if
(
load_
firm
ware
==
'y'
):
# Load
firm
ware to FPGA
load_
gateware
=
raw_input
(
'Do you want to load the gate
ware? [y,n]'
)
if
(
load_
gate
ware
==
'y'
):
# Load
gate
ware to FPGA
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
if
(
'y'
==
raw_input
(
'Test
firm
ware? [y,n]'
)):
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha_test.bin'
;
if
(
'y'
==
raw_input
(
'Test
gate
ware? [y,n]'
)):
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha_test.bin'
;
else
:
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
tests/test15.py
View file @
e6c22156
...
...
@@ -27,7 +27,7 @@ from PAGE.SineWaveform import *
"""
test15: Test trigger configurations
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
# Calibration box vendor and product IDs
...
...
@@ -54,20 +54,20 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
ADC_FS
=
10
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
def
load_
firm
ware
(
default_directory
):
print
"Load
firm
ware to FPGA"
def
load_
gate
ware
(
default_directory
):
print
"Load
gate
ware to FPGA"
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
def
disconnect_channels
(
fmc
):
...
...
@@ -176,19 +176,19 @@ def plot_ch(data, ylimit, trig_level=0):
def
main
(
default_directory
=
'.'
):
# Load
firm
ware
load_
firmware
=
raw_input
(
'Do you want to load the firm
ware? [y,n]'
)
if
(
load_
firm
ware
==
'y'
):
# Load
firm
ware to FPGA
# Load
gate
ware
load_
gateware
=
raw_input
(
'Do you want to load the gate
ware? [y,n]'
)
if
(
load_
gate
ware
==
'y'
):
# Load
gate
ware to FPGA
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
if
(
'y'
==
raw_input
(
'Test
firm
ware? [y,n]'
)):
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha_test.bin'
;
if
(
'y'
==
raw_input
(
'Test
gate
ware? [y,n]'
)):
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha_test.bin'
;
else
:
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
# Objects declaration
...
...
tests/test16.py
View file @
e6c22156
...
...
@@ -26,7 +26,7 @@ from PAGE.SineWaveform import *
"""
test16: Test analogue front-end frequency response
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
# Calibration box vendor and product IDs
...
...
@@ -57,15 +57,15 @@ STOP_FREQ = 80E6
STEP_FREQ
=
500E3
def
load_
firm
ware
(
default_directory
):
print
(
'Load
firm
ware to FPGA'
)
def
load_
gate
ware
(
default_directory
):
print
(
'Load
gate
ware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
@@ -156,14 +156,14 @@ def digital2volt(value, full_scale, nb_bit):
def
main
(
default_directory
=
'.'
):
# Load
firm
ware to FPGA
# Load
gate
ware to FPGA
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha_test.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha_test.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
tests/test17.py
View file @
e6c22156
...
...
@@ -36,7 +36,7 @@ from PAGE.SineWaveform import *
"""
test17: Plot all channels
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
GN4124_CSR
=
0x0
...
...
@@ -57,7 +57,7 @@ DAC_SET_SLEEP = 0.01
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
2000
POST_TRIG_SAMPLES
=
50000
...
...
@@ -66,7 +66,7 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
DMA_LENGTH
=
4096
# in bytes
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
...
...
@@ -192,18 +192,18 @@ def main (default_directory = '.'):
# Constants declaration
TEST_NB
=
19
EXPECTED_BITSTREAM_TYPE
=
0x1
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
carrier
=
fmc_adc_spec
.
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
fmc
=
fmc_adc
.
CFmcAdc100m
(
spec
)
...
...
@@ -214,7 +214,7 @@ def main (default_directory = '.'):
sine
=
SineWaveform
()
box
=
calibr_box
.
CCalibr_box
(
box_tty
[
0
])
# Work-around to make dma work with sdb
firm
ware
# Work-around to make dma work with sdb
gate
ware
#carrier.gnum.set_local_bus_freq(200)
print
"GN4124 local bus freq: "
,
carrier
.
gnum
.
get_local_bus_freq
()
...
...
tests/test19.py
View file @
e6c22156
...
...
@@ -37,7 +37,7 @@ from PAGE.SineWaveform import *
"""
test19: Calibration
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
NB_CHANNELS
=
4
...
...
@@ -55,7 +55,7 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
...
...
@@ -303,7 +303,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test19_2.py
View file @
e6c22156
...
...
@@ -27,7 +27,7 @@ from PAGE.SineWaveform import *
"""
test19_2: Calibration (recursive approach)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
GN4124_CSR
=
0x0
...
...
@@ -48,7 +48,7 @@ DAC_SET_SLEEP = 0.1
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
1000
POST_TRIG_SAMPLES
=
100000
...
...
@@ -57,20 +57,20 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
DMA_LENGTH
=
4096
# in bytes
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
def
load_
firm
ware
(
default_directory
):
print
(
'Load
firm
ware to FPGA'
)
def
load_
gate
ware
(
default_directory
):
print
(
'Load
gate
ware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha_test.bin'
;
path_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha_test.bin'
;
firm
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
firm
ware
)
print
firm
ware_loader
+
' '
+
bitstream
os
.
system
(
firm
ware_loader
+
' '
+
bitstream
)
gate
ware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_
gate
ware
)
print
gate
ware_loader
+
' '
+
bitstream
os
.
system
(
gate
ware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
...
...
@@ -255,8 +255,8 @@ def calc_od(Vm1, Vm2, Vm3, Vm4, Vref1):
def
main
(
default_directory
=
'.'
):
# Load
firm
ware to FPGA
load_
firm
ware
(
default_directory
)
# Load
gate
ware to FPGA
load_
gate
ware
(
default_directory
)
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
...
...
tests/test19_eeprom.py
View file @
e6c22156
...
...
@@ -20,7 +20,7 @@ import fmc_adc
"""
test19_eeprom: Test eeprom data formatting
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
tests/test20.py
View file @
e6c22156
...
...
@@ -40,7 +40,7 @@ from ctypes import *
"""
test20: Calibration verification (max error in LSB)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
Requires test19.py to run before to get calibration data.
Requires test23.py to run before to write the calibration data to the FMC EEPROM
"""
...
...
@@ -54,7 +54,7 @@ DAC_SET_SLEEP = 0.01
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
100
POST_TRIG_SAMPLES
=
100000
...
...
@@ -62,7 +62,7 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
...
...
@@ -258,7 +258,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test22.py
View file @
e6c22156
...
...
@@ -134,7 +134,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
22
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -155,16 +155,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test23.py
View file @
e6c22156
...
...
@@ -34,7 +34,7 @@ test23: Write IPMI information and calibration data to FMC EEPROM.
This is done using gensdbfs tool.
Serial number and calibration data are taken from text files.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
Requires test19.py to run before to get calibration data.
"""
...
...
tests/test25.py
View file @
e6c22156
...
...
@@ -40,7 +40,7 @@ from ctypes import *
"""
test25: Calibration verification (max error in
%
FS)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
Requires test19.py to run before to get calibration data.
Requires test23.py to run before to write the calibration data to the FMC EEPROM
"""
...
...
@@ -54,7 +54,7 @@ DAC_SET_SLEEP = 0.01
ACQ_TIMEOUT
=
10
MAX_
FIRM
WARE_RELOAD
=
10
MAX_
GATE
WARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
100
POST_TRIG_SAMPLES
=
100000
...
...
@@ -62,7 +62,7 @@ NB_SHOTS = 1
ACQ_LENGTH
=
50000
# in samples
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
...
...
@@ -267,7 +267,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test26.py
View file @
e6c22156
...
...
@@ -31,7 +31,7 @@ from fmc_adc import *
"""
test26: Read FMC EEPROM
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -54,7 +54,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test27.py
View file @
e6c22156
...
...
@@ -122,7 +122,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
27
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha_gnum_hang_patch.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha_gnum_hang_patch.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -135,16 +135,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
#print "Loading FMC ADC
firm
ware: %s\n" % FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
#print "Loading FMC ADC
gate
ware: %s\n" % FMC_ADC_BITSTREAM
#if(os.path.isfile(FMC_ADC_BITSTREAM)):
# spec.load_
firm
ware(FMC_ADC_BITSTREAM)
# spec.load_
gate
ware(FMC_ADC_BITSTREAM)
# time.sleep(2)
#else:
# raise PtsCritical("
Firm
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# raise PtsCritical("
Gate
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test28.py
View file @
e6c22156
...
...
@@ -56,7 +56,7 @@ LOAD_BITSTREAM = True
PLOT_ACQ
=
True
# Gateware
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
EXPECTED_BITSTREAM_TYPE
=
0x0
# Calibration box
...
...
@@ -79,7 +79,7 @@ MEMORY_SIZE = 2**28/(NB_CHANNELS * CHANNEL_BYTES) # samples
MULTISHOT_MAX_SIZE
=
2
**
11
# samples
SAMP_FREQ
=
100E6
# Hz
RANGES
=
{
'10V'
:
10.0
,
'1V'
:
1.0
,
'100mV'
:
0.1
}
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
firm
ware
ADC_NBITS
=
16
# ADC chip is 14 bits, but shifted to 16 bits in the
gate
ware
DAC_NBITS
=
16
DAC_FS
=
10
# DAC full scale range is 10V
CALIBR_BIN_FILENAME
=
"calibration_data.bin"
...
...
@@ -523,18 +523,18 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
# Load FMC ADC
gate
ware
if
LOAD_BITSTREAM
:
bitstream_path
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
bitstream_path
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
bitstream_path
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test29.py
View file @
e6c22156
...
...
@@ -31,7 +31,7 @@ from fmc_adc import *
"""
test29: Checks FMC EEPROM for existing data
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
tests/test30.py
View file @
e6c22156
...
...
@@ -35,7 +35,7 @@ from PAGE.SineWaveform import *
"""
test30: Test software reset.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -134,7 +134,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
30
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -155,16 +155,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test31.py
View file @
e6c22156
...
...
@@ -39,7 +39,7 @@ test31: Fix EEPROM content:
Serial number and manufacturing date are taken from the wrong EEPROM.
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
,
offset
=
"0x1000"
,
filename
=
"calibration.sdb"
):
...
...
tests/test32.py
View file @
e6c22156
...
...
@@ -37,7 +37,7 @@ import scipy.fftpack as fftpack
"""
test32: Test decimation
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
LOAD_BITSTREAM
=
False
...
...
@@ -185,7 +185,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
32
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -206,14 +206,14 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
# Load FMC ADC
gate
ware
if
LOAD_BITSTREAM
==
True
:
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test33.py
View file @
e6c22156
...
...
@@ -31,7 +31,7 @@ from fmc_adc import *
"""
test33: Write FMC EEPROM
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -54,7 +54,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test34.py
View file @
e6c22156
...
...
@@ -30,7 +30,7 @@ from fmc_adc import *
"""
test34: Test interrupts (EIC + VIC)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -53,7 +53,7 @@ def main (default_directory = '.'):
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test35.py
View file @
e6c22156
...
...
@@ -34,7 +34,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
35
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -53,13 +53,13 @@ def main (default_directory='.'):
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC
firm
ware
#print "Loading FMC ADC
firm
ware: %s\n" % FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
#print "Loading FMC ADC
gate
ware: %s\n" % FMC_ADC_BITSTREAM
#if(os.path.isfile(FMC_ADC_BITSTREAM)):
# spec.load_
firm
ware(FMC_ADC_BITSTREAM)
# spec.load_
gate
ware(FMC_ADC_BITSTREAM)
# time.sleep(2)
#else:
# raise PtsCritical("
Firm
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# raise PtsCritical("
Gate
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# Carrier object declaration (SPEC board specific part)
try
:
...
...
tests/test36.py
View file @
e6c22156
...
...
@@ -29,7 +29,7 @@ from fmc_adc import *
"""
test36: Test SDB records
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -37,7 +37,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
36
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -56,13 +56,13 @@ def main (default_directory='.'):
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC
firm
ware
#print "Loading FMC ADC
firm
ware: %s\n" % FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
#print "Loading FMC ADC
gate
ware: %s\n" % FMC_ADC_BITSTREAM
#if(os.path.isfile(FMC_ADC_BITSTREAM)):
# spec.load_
firm
ware(FMC_ADC_BITSTREAM)
# spec.load_
gate
ware(FMC_ADC_BITSTREAM)
# time.sleep(2)
#else:
# raise PtsCritical("
Firm
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# raise PtsCritical("
Gate
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# Carrier object declaration (SPEC board specific part)
try
:
...
...
tests/test37.py
View file @
e6c22156
...
...
@@ -35,7 +35,7 @@ from PAGE.SineWaveform import *
"""
test37: Test trigger timetags (single and multi shot modes)
Note: Requires test00.py to run first to load the
firm
ware!
Note: Requires test00.py to run first to load the
gate
ware!
"""
...
...
@@ -132,7 +132,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
37
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -155,16 +155,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test38.py
View file @
e6c22156
...
...
@@ -26,7 +26,7 @@ from fmc_adc_spec import *
"""
test38: Load
firm
ware, try to access to an un-mapped wishbone address -> the host shouldn't hang!
test38: Load
gate
ware, try to access to an un-mapped wishbone address -> the host shouldn't hang!
"""
def
main
(
default_directory
=
'.'
):
...
...
@@ -34,8 +34,8 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
38
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
#FMC_ADC_BITSTREAM = '../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha_test.bin'
#FMC_ADC_BITSTREAM = '../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha_test.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -54,13 +54,13 @@ def main (default_directory='.'):
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
try
:
...
...
tests/test39.py
View file @
e6c22156
...
...
@@ -162,7 +162,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
39
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -188,16 +188,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test40.py
View file @
e6c22156
...
...
@@ -204,7 +204,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
40
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -230,16 +230,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test41.py
View file @
e6c22156
...
...
@@ -208,7 +208,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
41
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -234,16 +234,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test42.py
View file @
e6c22156
...
...
@@ -36,7 +36,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
42
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -48,16 +48,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
#print "Loading FMC ADC
firm
ware: %s\n" % FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
#print "Loading FMC ADC
gate
ware: %s\n" % FMC_ADC_BITSTREAM
#if(os.path.isfile(FMC_ADC_BITSTREAM)):
# spec.load_
firm
ware(FMC_ADC_BITSTREAM)
# spec.load_
gate
ware(FMC_ADC_BITSTREAM)
# time.sleep(2)
#else:
# raise PtsCritical("
Firm
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# raise PtsCritical("
Gate
ware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test43.py
View file @
e6c22156
...
...
@@ -159,7 +159,7 @@ def main (default_directory='.'):
# Constants declaration
TEST_NB
=
43
FMC_ADC_BITSTREAM
=
'../
firm
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
'../
gate
wares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
...
...
@@ -185,16 +185,16 @@ def main (default_directory='.'):
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC
firm
ware
print
"Loading FMC ADC
firm
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
# Load FMC ADC
gate
ware
print
"Loading FMC ADC
gate
ware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
if
(
os
.
path
.
isfile
(
FMC_ADC_BITSTREAM
)):
spec
.
load_
firm
ware
(
FMC_ADC_BITSTREAM
)
spec
.
load_
gate
ware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firm
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
raise
PtsCritical
(
"
Gate
ware file
\"
%
s
\"
is missing, test stopped."
%
FMC_ADC_BITSTREAM
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the
firm
ware is loaded.
# Used to check that the
gate
ware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
...
...
tests/test_loader_lib.py
View file @
e6c22156
...
...
@@ -46,21 +46,21 @@ CTRL_DAC_CLR_N = (1<<2)
def
main
(
default_directory
=
'.'
):
# Old way of loading the
firm
ware
# Old way of loading the
gate
ware
"""
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_
firmware = '../firm
wares/spec_fmcadc100m14b4cha.bin';
path_
gateware = '../gate
wares/spec_fmcadc100m14b4cha.bin';
firm
ware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_
firm
ware)
print
firm
ware_loader + ' ' + bitstream
os.system(
firm
ware_loader + ' ' + bitstream )
gate
ware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_
gate
ware)
print
gate
ware_loader + ' ' + bitstream
os.system(
gate
ware_loader + ' ' + bitstream )
time.sleep(2);
"""
fmc_adc_addr
=
'1a39:0004/1a39:0004@000b:0000'
fmc_adc_
firmware
=
'../firm
wares/spec_fmcadc100m14b4cha.bin'
fmc_adc_
gateware
=
'../gate
wares/spec_fmcadc100m14b4cha.bin'
# SPEC object declaration
spec
=
rr
.
Gennum
()
...
...
@@ -71,13 +71,13 @@ def main (default_directory='.'):
print
"
%10
s: 0x
%04
X"
%
(
name
,
value
)
spec
.
bind
(
fmc_adc_addr
)
# Loads
firm
ware
print
"Loading
firm
ware"
if
(
os
.
path
.
isfile
(
fmc_adc_
firm
ware
)):
spec
.
load_
firmware
(
fmc_adc_firm
ware
)
# Loads
gate
ware
print
"Loading
gate
ware"
if
(
os
.
path
.
isfile
(
fmc_adc_
gate
ware
)):
spec
.
load_
gateware
(
fmc_adc_gate
ware
)
time
.
sleep
(
2
)
else
:
raise
PtsCritical
(
"
Firmware file
\"
%
s
\"
is missing, test stopped."
%
fmc_adc_firm
ware
)
raise
PtsCritical
(
"
Gateware file
\"
%
s
\"
is missing, test stopped."
%
fmc_adc_gate
ware
)
# Others objects declaration
carrier_csr
=
csr
.
CCSR
(
spec
,
CARRIER_CSR
)
...
...
@@ -86,7 +86,7 @@ def main (default_directory='.'):
bitstream_type
=
carrier_csr
.
rd_reg
(
CSR_BSTM_TYPE
)
print
(
'bitstream type:
%.8
X'
)
%
bitstream_type
if
(
bitstream_type
==
0xFFFFFFFF
):
raise
PtsCritical
(
"
Firm
ware not properly loaded."
)
raise
PtsCritical
(
"
Gate
ware not properly loaded."
)
if
(
bitstream_type
!=
0x1
):
raise
PtsCritical
(
"Wrong bitstream type."
)
...
...
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