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FMC ADC 100M 14b 4cha - Testing
Commit e9fb39c4 authored by Matthieu Cattin's avatar Matthieu Cattin
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Bitstream and mezzanine presence checked in fmc_adc_spec module init. 

Test00 modified consequently.
Add test time measurement.
parent e0e1f378
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Showing with 39 additions and 23 deletions
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @ e9fb39c4
......@@ -128,8 +128,9 @@ class CFmcAdc100mSpec:
#======================================================================
# Class initialisation
def __init__(self, bus):
def __init__(self, bus, bs_type):
self.bus = bus
# Objects declaration
self.dma_csr = CCSR(self.bus, self.GNUM_DMA_CSR_ADDR)
self.gnum = CGN4124(self.bus, self.dma_csr)
......@@ -138,9 +139,21 @@ class CFmcAdc100mSpec:
self.csr = CCSR(self.bus, self.CSR_ADDR)
self.utc_core = CCSR(self.bus, self.UTC_CORE_ADDR)
self.irq_controller = CCSR(self.bus, self.IRQ_CONTROLLER_ADDR)
# Get physical addresses of the pages for DMA transfer
self.dma_pages = self.gnum.get_physical_addr()
# Check if the expected bitstream loaded
bs = self.get_bitstream_type()
if(bs == 0xFFFFFFFF):
raise FmcAdc100mSpecOperationError("Bitstream not properly loaded.")
if(bs != bs_type):
raise FmcAdc100mSpecOperationError("Wrong bitsream. Excpect:0x%08X, Read:0x%08X" % (bs_type, bs))
# Ckeck if a mezzanine is present
if(not self.get_fmc_presence()):
raise FmcAdc100mSpecOperationError("Mezzanine not present or PRSNT_M2C_L line faulty.")
#======================================================================
# Generic functions
......@@ -212,8 +225,9 @@ class CFmcAdc100mSpec:
return self.get_reg(self.csr, self.CSR, 'CTRL')
# Get FMC presence state
# 1 = mezzanine present, 0 = no nezzanine
def get_fmc_presence(self):
return self.get_field(self.csr, self.CSR, 'STAT', 'FMC_PRES')
return not self.get_field(self.csr, self.CSR, 'STAT', 'FMC_PRES')
# Get Gennum core P2L PLL lock state
def get_p2l_pll_lock(self):
......
test/fmcadc100m14b4cha/python/test00.py
View file @ e9fb39c4
......@@ -32,46 +32,48 @@ test00: Load firmware, verify firmware type and test mezzanine presence line.
def main (default_directory='.'):
# Constants declaration
FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_ADC_BITSTREAM = '../firmwares/spec_fmcadc100m14b4cha.bin'
EXPECTED_BITSTREAM_TYPE = 0x1
start_test_time = time.time()
print "================================================================================"
print "Test00 start\n"
# SPEC object declaration
print "Loading hardware access library and opening device.\n"
spec = rr.Gennum()
# Bind SPEC object to FMC ADC card
for name, value in spec.parse_addr(FMC_ADC_ADDR).iteritems():
print "%9s:0x%04X"%(name, value)
#for name, value in spec.parse_addr(FMC_ADC_ADDR).iteritems():
# print "%9s:0x%04X"%(name, value)
spec.bind(FMC_ADC_ADDR)
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC firmware
print "\nLoading FMC ADC firmware: %s" % FMC_ADC_BITSTREAM
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
spec.load_firmware(FMC_ADC_BITSTREAM)
time.sleep(2)
# Carrier object declaration (SPEC board specific part)
carrier = CFmcAdc100mSpec(spec)
try:
carrier = CFmcAdc100mSpec(spec, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSpecOperationError as e:
raise PtsCritical("The test is stopped due to the following critical error: " + e)
# Check bitsteam type
# Print bitsteam type
bitstream_type = carrier.get_bitstream_type()
print('\nBitstream type:%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsCritical ("Firmware not properly loaded.")
if(bitstream_type != EXPECTED_BITSTREAM_TYPE):
raise PtsCritical ("Wrong bitstream type.")
else:
print "Bitstream type OK."
# Dump carrier CSR to log
print('Bitstream type:0x%.8X') % bitstream_type
print "Bitstream type OK.\n"
# Print carrier CSR registers
carrier.print_csr()
# Check mezzanine presence flag
if(carrier.get_fmc_presence()):
raise PtsCritical ("Mezzanine not present or PRSNT_M2C_L line faulty.")
else:
print "Mezzanine present, tests can continue."
print "End of test00\n"
print "================================================================================"
end_test_time = time.time()
print "Test00 elapsed time: %.2f seconds\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
......
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