-> fmc_eic and timetag core moved to mezzanine (behind bridge).
-> ddr addr and data (for svec) moved.

fmc_adc, many tests: Add sdb to fmc_adc class, use csr class for timetags reading, change trigger position to byte address (was sample address).

Was using natural log instead of base 10 log. In python log() is natural log!
Tolerance values were converted using: new = 20*log10(e^(old/20))

Note that this wasn't affecting the test as the tolerance values were calculated
with the same (wrong) formula.