`define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1000
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1e00
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1500
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1ff0
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
`define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1f00
`define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
`define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1ff0
`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1fe0
`define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
`define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900
`define ADDR_MASK_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1f80
`define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
