Commit 2be437da authored by Matthieu Cattin's avatar Matthieu Cattin

syn: spec-fmc-adc firmware release 3.0

parent 69754630
......@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "dce448c21e7f9426dd5b39d1ef1d0496",
syn_commit_id => "697546304b7a1890aba8d6effd935a0f",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130729",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140116",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -70,7 +70,7 @@ package sdb_meta_pkg is
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131203", -- yyyymmdd
date => x"20140116", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jul 29 10:58:04 2013
Mapped Date : Thu Jan 16 17:57:07 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,876 out of 54,576 12%
Number used as Flip Flops: 6,876
Number of Slice Registers: 6,698 out of 54,576 12%
Number used as Flip Flops: 6,698
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,566 out of 27,288 20%
Number used as logic: 5,147 out of 27,288 18%
Number using O6 output only: 3,316
Number using O5 output only: 286
Number using O5 and O6: 1,545
Number of Slice LUTs: 5,758 out of 27,288 21%
Number used as logic: 5,404 out of 27,288 19%
Number using O6 output only: 3,644
Number using O5 output only: 368
Number using O5 and O6: 1,392
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 417
Number with same-slice register load: 404
Number with same-slice carry load: 13
Number used exclusively as route-thrus: 352
Number with same-slice register load: 328
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,422 out of 6,822 35%
Nummber of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,669
Number with an unused Flip Flop: 1,694 out of 7,669 22%
Number with an unused LUT: 2,103 out of 7,669 27%
Number of fully used LUT-FF pairs: 3,872 out of 7,669 50%
Number of unique control sets: 265
Number of occupied Slices: 2,468 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,910
Number with an unused Flip Flop: 1,939 out of 7,910 24%
Number with an unused LUT: 2,152 out of 7,910 27%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48%
Number of unique control sets: 237
Number of slice register sites lost
to control set restrictions: 682 out of 54,576 1%
to control set restrictions: 548 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,8 +63,8 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 27 out of 116 23%
Number of RAMB8BWERs: 2 out of 232 1%
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 4 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.76
Average Fanout of Non-Clock Nets: 3.80
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 42 secs
Total CPU time to MAP completion (all processors): 4 mins 42 secs
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 52 secs
Total CPU time to MAP completion (all processors): 4 mins 43 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N862,
N864,
N798,
N800,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment