Commit 4a8d8c1a authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Remove "reserved" fields from svec/spec carrier csr cores.

parent 1cdf5160
......@@ -66,11 +66,6 @@ System clock PLL status
@code{DDR3_CAL_DONE}
@tab @code{X} @tab
DDR3 calibration status
@item @code{31...4}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -78,7 +73,6 @@ Reserved
@item @code{p2l_pll_lck} @tab 0: not locked@*1: locked.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr3_cal_done} @tab 0: not done@*1: done.
@item @code{reserved} @tab Ignore on read, write with 0's.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -98,18 +92,12 @@ Red LED
@code{DAC_CLR_N}
@tab @code{0} @tab
DAC clear
@item @code{31...3}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
......@@ -120,14 +108,8 @@ Controls software reset of the mezzanine including the ddr interface and the tim
@code{FMC0_N}
@tab @code{X} @tab
State of the reset line
@item @code{31...1}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
......@@ -71,11 +71,6 @@ DDR3 bank 4 calibration status
@code{DDR1_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 5 calibration status
@item @code{31...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -84,7 +79,6 @@ Reserved
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@item @code{reserved} @tab Ignore on read, write with 0's.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -94,16 +88,10 @@ Reserved
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
......@@ -119,15 +107,9 @@ State of the FMC 1 reset line
@code{FMC1_N}
@tab @code{X} @tab
State of the FMC 2 reset line
@item @code{31...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jan 14 11:45:49 2014
-- Created : Wed Apr 23 10:05:23 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -41,22 +41,16 @@ entity carrier_csr is
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_csr_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
carrier_csr_rst_fmc0_n_load_o : out std_logic
);
end carrier_csr;
......@@ -65,8 +59,6 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -97,9 +89,7 @@ begin
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -129,7 +119,34 @@ begin
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
......@@ -137,21 +154,77 @@ begin
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -174,19 +247,14 @@ begin
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -197,15 +197,12 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic;
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
carrier_csr_rst_fmc0_n_load_o : out std_logic
);
end component carrier_csr;
......@@ -729,15 +726,12 @@ begin
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_csr_stat_reserved_i => (others => '0'),
carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load,
carrier_csr_rst_reserved_o => open
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load
);
-- Unused wishbone signals
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Jan 14 11:45:49 2014
* Created : Wed Apr 23 10:05:23 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -65,12 +65,6 @@
/* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Status */
#define CARRIER_CSR_STAT_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define CARRIER_CSR_STAT_RESERVED_SHIFT 4
#define CARRIER_CSR_STAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define CARRIER_CSR_STAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */
......@@ -82,23 +76,11 @@
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Control */
#define CARRIER_CSR_CTRL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define CARRIER_CSR_CTRL_RESERVED_SHIFT 3
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(1, 31)
#define CARRIER_CSR_RST_RESERVED_SHIFT 1
#define CARRIER_CSR_RST_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 1, 31)
#define CARRIER_CSR_RST_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 1, 31)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
......
......@@ -305,23 +305,6 @@ carrier_csr_stat_ddr3_cal_done_i
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_reserved_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -407,23 +390,6 @@ carrier_csr_ctrl_dac_clr_n_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_reserved_o[28:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -503,23 +469,6 @@ carrier_csr_rst_fmc0_n_load_o
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_reserved_o[30:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -853,29 +802,29 @@ STAT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -907,29 +856,29 @@ RESERVED[27:20]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -961,29 +910,29 @@ RESERVED[19:12]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1015,8 +964,17 @@ RESERVED[11:4]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE
......@@ -1029,15 +987,6 @@ P2L_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -1058,10 +1007,6 @@ SYS_PLL_LCK
DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="CTRL"></a>
<h3><a name="sect_3_3">3.3. Control</a></h3>
......@@ -1127,29 +1072,29 @@ CTRL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[28:21]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1181,29 +1126,29 @@ RESERVED[28:21]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[20:13]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1235,29 +1180,29 @@ RESERVED[20:13]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[12:5]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>