Commit 691b2d75 authored by Matthieu Cattin's avatar Matthieu Cattin

hdl, doc, sim: Fix sdb bridge offset address, add config ok flag, update doc in progress.

parent 7f7c711b
......@@ -371,6 +371,121 @@
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......@@ -180,7 +180,12 @@ SerDes PLL status
@code{SERDES_SYNCED}
@tab @code{X} @tab
SerDes synchronization status
@item @code{31...5}
@item @code{5}
@tab R/O @tab
@code{ACQ_CFG}
@tab @code{X} @tab
Acquisition configuration status
@item @code{31...6}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
......@@ -188,9 +193,10 @@ Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: DECR_SHOT@*6: illegal@*7: illegal
@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: TRIG_TAG@*6: DECR_SHOT@*7: illegal
@item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked
@item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{} Shot number > 0@*@bullet{} Post-trigger sample > 0
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{trig_cfg} - Trigger configuration
......@@ -240,7 +246,7 @@ Threshold for internal trigger
@item @code{sw_trig_en} @tab 0: disable@*1: enable
@item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{trig_dly} - Trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -321,7 +327,7 @@ Pre-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pre_samples} @tab Number of requested pre-trigger samples
@item @code{pre_samples} @tab Number of requested pre-trigger samples (>1).
@end multitable
@regsection @code{post_samples} - Post-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -334,7 +340,7 @@ Post-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{post_samples} @tab Number of requested post-trigger samples
@item @code{post_samples} @tab Number of requested post-trigger samples (>1).
@end multitable
@regsection @code{samples_cnt} - Samples counter
@multitable @columnfractions .10 .10 .15 .10 .55
......
......@@ -420,6 +420,10 @@ Those two counters are accessible in read/write mode via registers.
To time-tag the events, the ADC core sends pulses to the time-tagging core.
The following events are time-tagged; trigger, acquisition start, acquisition stop and acquisition end.
@quotation Note
The trigger time tag corresponds to the moment when the acquisition FSM leaves the @code{WAIT_TRIG} state.
@end quotation
@quotation Note
In this release, the meta-data register is NOT used, set to zero.
@end quotation
......@@ -876,7 +880,11 @@ The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b
The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state.
@quotation Note
In addition to the requested pre/post-trigger samples, an addition sample, corresponding to the trigger, will be recoded.
The number of pre-trigger sample can be zero, but there @b{must} be at least one post-trigger sample.
@end quotation
@quotation Note
In addition to the requested pre/post-trigger samples, an additional sample, corresponding to the trigger, will be recoded.
@end quotation
@c --------------------------------------------------------------------------
......
This diff is collapsed.
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Wed Aug 7 17:44:15 2013
-- Created : Tue Dec 17 09:57:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -51,8 +51,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sta_serdes_pll_i : in std_logic;
-- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register'
fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for BIT field: 'Acquisition configuration status' in reg: 'Status register'
fmc_adc_core_sta_acq_cfg_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
fmc_adc_core_sta_reserved_i : in std_logic_vector(26 downto 0);
fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
......@@ -429,7 +431,8 @@ begin
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(31 downto 5) <= fmc_adc_core_sta_reserved_i;
rddata_reg(5) <= fmc_adc_core_sta_acq_cfg_i;
rddata_reg(31 downto 6) <= fmc_adc_core_sta_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
......@@ -745,6 +748,7 @@ begin
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
-- Acquisition configuration status
-- Reserved
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Wed Aug 7 17:44:15 2013
* Created : Tue Dec 17 09:57:20 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -77,11 +77,14 @@
/* definitions for field: SerDes synchronization status in reg: Status register */
#define FMC_ADC_CORE_STA_SERDES_SYNCED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Acquisition configuration status in reg: Status register */
#define FMC_ADC_CORE_STA_ACQ_CFG WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Reserved in reg: Status register */
#define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define FMC_ADC_CORE_STA_RESERVED_SHIFT 5
#define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
#define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(6, 26)
#define FMC_ADC_CORE_STA_RESERVED_SHIFT 6
#define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 26)
#define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 26)
/* definitions for register: Trigger configuration */
......
......@@ -809,7 +809,24 @@ fmc_adc_core_sta_serdes_synced_i
</td>
<td class="td_pblock_right">
fmc_adc_core_sta_reserved_i[26:0]
fmc_adc_core_sta_acq_cfg_i
</td>
<td class="td_arrow_right">
&larr;
</td>
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<tr>
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</td>
<td class="td_pblock_left">
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<td class="td_pblock_right">
fmc_adc_core_sta_reserved_i[25:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2849,7 +2866,7 @@ STA
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[26:19]
RESERVED[25:18]
</td>
<td >
......@@ -2903,7 +2920,7 @@ RESERVED[26:19]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[18:11]
RESERVED[17:10]
</td>
<td >
......@@ -2957,7 +2974,7 @@ RESERVED[18:11]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[10:3]
RESERVED[9:2]
</td>
<td >
......@@ -3010,8 +3027,11 @@ RESERVED[10:3]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[2:0]
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_CFG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
......@@ -3030,9 +3050,6 @@ FSM[2:0]
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -3040,7 +3057,7 @@ FSM[2:0]
<li><b>
FSM
</b>[<i>read-only</i>]: State machine status
<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: DECR_SHOT<br>6: illegal<br>7: illegal
<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: TRIG_TAG<br>6: DECR_SHOT<br>7: illegal
<li><b>
SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status
......@@ -3050,6 +3067,10 @@ SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
ACQ_CFG
</b>[<i>read-only</i>]: Acquisition configuration status
<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
......@@ -3334,7 +3355,7 @@ RESERVED
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data
<br>Treated as binary two's complement and compared to raw ADC data.
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
......@@ -4888,7 +4909,7 @@ PRE_SAMPLES[7:0]
<li><b>
PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples
<br>Number of requested pre-trigger samples (>1).
</ul>
<a name="POST_SAMPLES"></a>
<h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3>
......@@ -5146,7 +5167,7 @@ POST_SAMPLES[7:0]
<li><b>
POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples
<br>Number of requested post-trigger samples (>1).
</ul>
<a name="SAMPLES_CNT"></a>
<h3><a name="sect_3_11">3.11. Samples counter</a></h3>
......
......@@ -86,7 +86,7 @@ peripheral {
field {
name = "State machine status";
description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: DECR_SHOT\n6: illegal\n7: illegal";
description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
prefix = "fsm";
type = SLV;
size = 3;
......@@ -112,12 +112,21 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Acquisition configuration status";
description = "0: Unauthorised acquisition configuration (will prevent acquisition to start)\n1: Valid acquisition configuration\n- Shot number > 0\n- Post-trigger sample > 0";
prefix = "acq_cfg";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 27;
size = 26;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -190,7 +199,7 @@ peripheral {
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
type = SLV;
size = 16;
......@@ -288,7 +297,7 @@ peripheral {
field {
name = "Pre-trigger samples";
description = "Number of requested pre-trigger samples";
description = "Number of requested pre-trigger samples (>1).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -302,7 +311,7 @@ peripheral {
field {
name = "Post-trigger samples";
description = "Number of requested post-trigger samples";
description = "Number of requested post-trigger samples (>1).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Aug 8 14:54:22 2013
-- Created : Wed Dec 11 11:55:04 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
......@@ -347,8 +347,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
name => "WB-FMC-ADC.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the parent interconnect
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00004000");
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......
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......@@ -7,14 +7,21 @@ files = ["testbench/gn412x_bfm.vhd",
"testbench/util.vhd",
"testbench/tb_spec.vhd",
"testbench/cmd_router1.vhd",
"../ip_cores/adc_sync_fifo.vhd",
"../ip_cores/multishot_dpram.vhd",
"../ip_cores/wb_ddr_fifo.vhd",
"../ip_cores/adc_serdes.vhd",
"../ip_cores/monostable/monostable_rtl.vhd",
"../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
"../ip_cores/utils/utils_pkg.vhd"]
"../../ip_cores/adc_sync_fifo.vhd",
"../../ip_cores/multishot_dpram.vhd",
"../../ip_cores/wb_ddr_fifo.vhd",
"../../ip_cores/adc_serdes.vhd",
"../../ip_cores/monostable/monostable_rtl.vhd",
"../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
"../../ip_cores/utils/utils_pkg.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl",
"testbench",
"sim_models/2048Mb_ddr3"]}
"sim_models/2048Mb_ddr3"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../../ip_cores"
......@@ -209,86 +209,106 @@ wait %d2000
-- onewire config
wr FF00000000001A04 F 007C0270
wr FF00000000001104 F 007C0270
wait %d100
wr FF00000000001A00 F 0000000A
wr FF00000000001100 F 0000000A
wait %d100
-- irq mask
wr FF00000000001508 F 0000000F
-- fmc eic set irq enable mask
wr FF00000000002004 F 00000003
-- dma eic set irq enable mask
wr FF00000000001404 F 00000003
-- vic set irq enable mask
wr FF00000000001308 F 00000003
-- vic config
wr FF00000000001300 F 00001777
-- release fmc reset
wr FF0000000000120C F 00000003
-- Set time-tag core seconds
wr FF00000000002100 F 00001234
-- Set time-tag core coarse time
wr FF00000000002104 F 00000000
-- trigger config (sw trig enable)
wr FF00000000001908 F 00000008
wr FF00000000005308 F 00000008
-- trigger config (hw int trig enable)
--wr FF00000000001908 F 00000004
--wr FF00000000005308 F 00000004
-- trigger config (int trig)
--wr FF00000000001908 F 02600004
--wr FF00000000005308 F 02600004
-- decimation factor = 1
wr FF0000000000191C F 00000001
wr FF0000000000531C F 00000001
-- pre-trig samples
wr FF00000000001920 F 00000100
wr FF00000000005320 F 00000000
-- post-trig samples
wr FF00000000001924 F 00001000
wr FF00000000005324 F 00000001
-- number of shots
wr FF00000000001914 F 00000001
wr FF00000000005314 F 00000003
-- Channel 1 gain
wr FF00000000001934 F 00008000
wr FF00000000005334 F 00008000
-- Channel 1 offset
wr FF00000000001938 F 00000000
wr FF00000000005338 F 00000000
-- Channel 2 gain
wr FF00000000001944 F 00008000
wr FF00000000005344 F 00008000
-- Channel 2 offset
wr FF00000000001948 F 00000000
wr FF00000000005348 F 00000000
-- Channel 3 gain
wr FF00000000001954 F 00008000
wr FF00000000005354 F 00008000
-- Channel 3 offset
wr FF00000000001958 F 00000000
wr FF00000000005358 F 00000000
-- Channel 4 gain
wr FF00000000001964 F 00008000
wr FF00000000005364 F 00008000
-- Channel 4 offset
wr FF00000000001968 F 00000000
wr FF00000000005368 F 00000000
-- Enable test data and sampling clock
--wr FF00000000001900 F 00000024
--wr FF00000000005300 F 00000024
-- Enable sampling clock
wr FF00000000001900 F 00000004
wr FF00000000005300 F 00000004
wait %d2000
-- start acquisition
--wr FF00000000001900 F 00000025
wr FF00000000001900 F 00000005
--wr FF00000000005300 F 00000025
wr FF00000000005300 F 00000005
wait %d800
-- sw trigger
wr FF00000000001910 F FFFFFFFF
wr FF00000000005310 F FFFFFFFF
wait %d800
-- stop acquisition
wr FF00000000001900 F 00000006
--wr FF00000000005300 F 00000006
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
wr FF00000000005310 F FFFFFFFF
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
wr FF00000000005310 F FFFFFFFF
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
--wr FF00000000005310 F FFFFFFFF
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
--wr FF00000000005310 F FFFFFFFF
wait %d1000
......@@ -316,11 +336,11 @@ wait %d3000