Maintenance scheduled 24th July -- expect downtime along that day

Commit b5785db9 authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Change interrupt scheme, now uses eic + vic. Changes in memory map.

parent e8eb12b4
......@@ -4,4 +4,5 @@ files = [
"fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd"]
This diff is collapsed.
......@@ -150,55 +150,7 @@ architecture rtl of fmc_adc_mezzanine is
constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4; -- Mezzanine onewire interface
-- Devices sdb description
constant c_ONEWIRE_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000007",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000602",
version => x"00000001",
date => x"20121116",
name => "WB-Onewire.Control ")));
constant c_I2C_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000606",
version => x"00000001",
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_SPI_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000607",
version => x"00000001",
date => x"20121116",
name => "WB-SPI.Control ")));
constant c_ADC_CSR_SDB_DEVICE : t_sdb_device := (
constant c_wb_adc_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -220,11 +172,11 @@ architecture rtl of fmc_adc_mezzanine is
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(
0 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_SPI_SDB_DEVICE, x"00001100"),
2 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001200"),
3 => f_sdb_embed_device(c_ADC_CSR_SDB_DEVICE, x"00001300"),
4 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001400")
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001100"),
2 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001200"),
3 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001300"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001400")
);
......
......@@ -4,4 +4,8 @@ TEX=../../../documentation/manuals/firmware/
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
\ No newline at end of file
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
/*
Register definitions for slave core: Interrupt controller
Register definitions for slave core: Fmc-adc enhanced interrupt controller
* File : irq_controller.h
* Author : auto-generated by wbgen2 from irq_controller.wb
* Created : Tue Jul 23 15:22:16 2013
* File : fmc_adc_eic.h
* Author : auto-generated by wbgen2 from fmc_adc_eic.wb
* Created : Wed Dec 4 09:44:26 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB
#define __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB
#ifndef __WBGEN2_REGDEFS_FMC_ADC_EIC_WB
#define __WBGEN2_REGDEFS_FMC_ADC_EIC_WB
#include <inttypes.h>
......@@ -33,61 +33,37 @@
/* definitions for register: Interrupt disable register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger interrupt in reg: Interrupt disable register */
#define EIC_EIC_IDR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt disable register */
#define EIC_EIC_IDR_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Trigger interrupt in reg: Interrupt enable register */
#define EIC_EIC_IER_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt enable register */
#define EIC_EIC_IER_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger interrupt in reg: Interrupt mask register */
#define EIC_EIC_IMR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt mask register */
#define EIC_EIC_IMR_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Trigger interrupt in reg: Interrupt status register */
#define EIC_EIC_ISR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt status register */
#define EIC_EIC_ISR_ACQ_END WBGEN2_GEN_MASK(1, 1)
PACKED struct IRQ_CTRL_WB {
PACKED struct EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
......
peripheral {
name = "Fmc-adc enhanced interrupt controller";
description = "Enhanced interrrupt controller for one fmc-adc mezzanine.";
hdl_entity = "fmc_adc_eic";
prefix = "fmc_adc_eic";
irq {
name = "Trigger interrupt";
description = "Trigger interrupt line (rising edge sensitive).";
prefix = "trig";
trigger = EDGE_RISING;
};
irq {
name = "End of acquisition interrupt";
description = "End of acquisition interrupt line (rising edge sensitive).";
prefix = "acq_end";
trigger = EDGE_RISING;
};
};
files = [
"spec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd",
"dma_eic.vhd",
"sdb_meta_pkg.vhd"]
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- IRQ controller
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: irq_controller (irq_controller.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity irq_controller is
port (
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Interrupt sources input, must be 1 clk_i tick long
irq_src_p_i : in std_logic_vector(31 downto 0);
-- IRQ pulse output
irq_p_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end irq_controller;
architecture rtl of irq_controller is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component irq_controller_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end component irq_controller_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal irq_en_mask : std_logic_vector(31 downto 0);
signal irq_pending : std_logic_vector(31 downto 0);
signal irq_pending_d : std_logic_vector(31 downto 0);
signal irq_pending_re : std_logic_vector(31 downto 0);
signal irq_src_rst : std_logic_vector(31 downto 0);
signal irq_src_rst_en : std_logic;
signal multi_irq : std_logic_vector(31 downto 0);
signal multi_irq_rst : std_logic_vector(31 downto 0);
signal multi_irq_rst_en : std_logic;
signal irq_p_or : std_logic_vector(32 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone interface to IRQ controller registers
------------------------------------------------------------------------------
cmp_irq_controller_regs : irq_controller_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq,
irq_ctrl_src_o => irq_src_rst,
irq_ctrl_src_i => irq_pending,
irq_ctrl_src_load_o => irq_src_rst_en,
irq_ctrl_en_mask_o => irq_en_mask
);
------------------------------------------------------------------------------
-- Register interrupt sources
-- IRQ is pending until a '1' is written to the corresponding bit
------------------------------------------------------------------------------
p_irq_src : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to irq_pending'length-1 loop
if rst_n_i = '0' then
irq_pending(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_en_mask(I) = '1' then
irq_pending(I) <= '1';
elsif irq_src_rst_en = '1' and irq_src_rst(I) = '1' then
irq_pending(I) <= '0';
end if;
end loop; -- I
end if;
end process p_irq_src;
------------------------------------------------------------------------------
-- Multiple interrupt detection
-- Rise a flag if an interrupt occurs while an irq is still pending
-- Write '1' to the flag to clear it
------------------------------------------------------------------------------
p_multi_irq_detect : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to multi_irq'length-1 loop
if rst_n_i = '0' then
multi_irq(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
multi_irq(I) <= '1';
elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
multi_irq(I) <= '0';
end if;
end loop; -- I
end if;
end process p_multi_irq_detect;
------------------------------------------------------------------------------
-- Generate IRQ output pulse
------------------------------------------------------------------------------
irq_p_or(0) <= '0';
l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
end generate l_irq_out_pulse;
p_irq_out_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_p_o <= '0';
else
irq_p_o <= irq_p_or(32);
end if;
end if;
end process p_irq_out_pulse;
end rtl;
......@@ -44,12 +44,12 @@ package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
......@@ -65,12 +65,12 @@ package sdb_meta_pkg is
syn_username => "mcattin ");
-- Integration record
constant c_SDB_INTEGRATION : t_sdb_integration := (
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00020000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130729", -- yyyymmdd
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131203", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
This diff is collapsed.
......@@ -6,6 +6,6 @@ carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
irq_controller_regs:
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
/*
Register definitions for slave core: GN4124 DMA enhanced interrupt controller
* File : dma_eic.h
* Author : auto-generated by wbgen2 from dma_eic.wb
* Created : Wed Dec 4 09:51:41 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
#define __WBGEN2_REGDEFS_DMA_EIC_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: DMA done interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: DMA done interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMA done interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: DMA done interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
PACKED struct DMA_EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
/*
Register definitions for slave core: IRQ controller registers
* File : irq_controller_regs.h
* Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Created : Tue Jul 23 16:04:41 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_IRQ_CONTROLLER_REGS_WB
#define __WBGEN2_REGDEFS_IRQ_CONTROLLER_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Multiple interrupt register */
/* definitions for register: Interrupt sources register */
/* definitions for register: Interrupt enable mask register */
PACKED struct IRQ_CTRL_WB {
/* [0x0]: REG Multiple interrupt register */
uint32_t MULTI_IRQ;
/* [0x4]: REG Interrupt sources register */
uint32_t SRC;
/* [0x8]: REG Interrupt enable mask register */
uint32_t EN_MASK;
};
#endif
This diff is collapsed.
peripheral {
name = "IRQ controller registers";
description = "Wishbone slave for registers related to IRQ controller";
hdl_entity = "irq_controller_regs";
prefix = "irq_ctrl";
reg {
name = "Multiple interrupt register";
description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "multi_irq";
field {
name = "Multiple interrupt";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Interrupt sources register ";
description = "Indicates the interrupt source.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "src";
field {
name = "Interrupt sources";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Interrupt enable mask register";
description = "Bit mask to independently enable interrupt sources.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "en_mask";
field {
name = "Interrupt enable mask";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
files = [
"svec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"irq_controller.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd",
"sdb_meta_pkg.vhd"]
......@@ -44,12 +44,12 @@ package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "svec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
......@@ -65,12 +65,12 @@ package sdb_meta_pkg is
syn_username => "mcattin ");
-- Integration record
constant c_SDB_INTEGRATION : t_sdb_integration := (
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131004", -- yyyymmdd
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131203", -- yyyymmdd
name => "svec_fmcadc100m14b "));
......
This diff is collapsed.
......@@ -5,7 +5,3 @@ TEX=../../../documentation/manuals/firmware/svec/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
irq_controller:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb