Commit b6f3ccb2 authored by Matthieu Cattin's avatar Matthieu Cattin

doc: Add some drawings, register docs and sdb tree descriptions.

parent fd92088c
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: disable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: disable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: enable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: enable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/O @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is enabled@*read 0: interrupt 'Trigger interrupt' is disabled
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is enabled@*read 0: interrupt 'End of acquisition interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/W @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@verbatim
integration: vid=0xCE42, did=0x47c786a2
wb crossbar: vid=0x0651, did=0xe6a542c9
wb bridge : vid=0x0651, did=0xeef0b198
vic : vid=0xCE42, did=0x00000013
onewire : vid=0xCE42, did=0x779c5443
spec_csr : vid=0xCE42, did=0x00000603
svec_csr : vid=0xCE42, did=0x00006603
timetag : vid=0xCE42, did=0x00000604
fmc_eic : vid=0xCE42, did=0x26ec6086
i2c : vid=0xCE42, did=0x123c5443
spi : vid=0xCE42, did=0xe503947e
adc_csr : vid=0xCE42, did=0x00000608
dma_eic : vid=0xCE42, did=0xd5735ab4
dma_ctrl : vid=0xCE42, did=0x00000601
ddr_addr : vid=0xCE42, did=0x10006611
ddr_data : vid=0xCE42, did=0x10006610
@end verbatim
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: disable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: disable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: enable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: enable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/O @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is enabled@*read 0: interrupt 'DMA done interrupt' is disabled
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is enabled@*read 0: interrupt 'DMA error interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/W @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- dma controller
0x1100 |-- onewire master
0x1200 |-- spec csr
0x1300 |-- vic
0x1400 |-- dma eic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c master
0x3100 | |-- spi master
0x3200 | |-- i2c master
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc-adc eic
0x3600 | |-- timetag core
@end verbatim
@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- i2c
0x1100 |-- onewire
0x1200 |-- svec csr
0x1300 |-- vic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c
0x3100 | |-- spi
0x3200 | |-- i2c
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc_eic
0x3600 | |-- timetag
0x4000 |-- ddr_addr (fmc slot 1)
0x5000 |-- ddr_data (fmc slot 1)
0x6000 |-- bridge (fmc slot 2) -> crossbar (sdb records)
0x7000 | |-- i2c
0x7100 | |-- spi
0x7200 | |-- i2c
0x7300 | |-- adc csr
0x7400 | |-- onewire
0x7500 | |-- fmc_eic
0x7600 | |-- timetag
0x8000 |-- ddr_addr (fmc slot 2)
0x9000 |-- ddr_data (fmc slot 2)
@end verbatim
This diff is collapsed.
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{CTL} @tab
VIC Control Register
@item @code{0x4} @tab
REG @tab
@code{RISR} @tab
Raw Interrupt Status Register
@item @code{0x8} @tab
REG @tab
@code{IER} @tab
Interrupt Enable Register
@item @code{0xc} @tab
REG @tab
@code{IDR} @tab
Interrupt Disable Register
@item @code{0x10} @tab
REG @tab
@code{IMR} @tab
Interrupt Mask Register
@item @code{0x14} @tab
REG @tab
@code{VAR} @tab
Vector Address Register
@item @code{0x18} @tab
REG @tab
@code{SWIR} @tab
Software Interrupt Register
@item @code{0x1c} @tab
REG @tab
@code{EOIR} @tab
End Of Interrupt Acknowledge Register
@item @code{0x20 - 0x3f}
@tab MEM @tab @code{IVT_RAM} @tab Interrupt Vector Table
@end multitable
@regsection @code{CTL} - VIC Control Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{ENABLE}
@tab @code{0} @tab
VIC Enable
@item @code{1}
@tab R/W @tab
@code{POL}
@tab @code{0} @tab
VIC output polarity
@item @code{2}
@tab R/W @tab
@code{EMU_EDGE}
@tab @code{0} @tab
Emulate Edge sensitive output
@item @code{18...3}
@tab R/W @tab
@code{EMU_LEN}
@tab @code{0} @tab
Emulated Edge pulse timer
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ENABLE} @tab @bullet{} 1: enables VIC operation@*@bullet{} 0: disables VIC operation
@item @code{POL} @tab @bullet{} 1: IRQ output is active high@*@bullet{} 0: IRQ output is active low
@item @code{EMU_EDGE} @tab @bullet{} 1: Forces a low pulse of @code{EMU_LEN} clock cycles at each write to @code{EOIR}. Useful for edge-only IRQ controllers such as Gennum.@*@bullet{} 0: Normal IRQ master line behavior
@item @code{EMU_LEN} @tab Length of the delay (in @code{clk_sys_i} cycles) between write to @code{EOIR} and re-assertion of @code{irq_master_o}.
@end multitable
@regsection @code{RISR} - Raw Interrupt Status Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{RISR}
@tab @code{X} @tab
Raw interrupt status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RISR} @tab Each bit reflects the current state of corresponding IRQ input line.@*@bullet{} read 1: interrupt line is currently active@*@bullet{} read 0: interrupt line is inactive
@end multitable
@regsection @code{IER} - Interrupt Enable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IER}
@tab @code{0} @tab
Enable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IER} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IDR} - Interrupt Disable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IDR}
@tab @code{0} @tab
Disable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IDR} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IMR} - Interrupt Mask Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IMR}
@tab @code{X} @tab
IRQ disabled/enabled
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IMR} @tab @bullet{} read 1: interrupt associated with read bit is enabled@*@bullet{} read 0: interrupt is disabled
@end multitable
@regsection @code{VAR} - Vector Address Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{VAR}
@tab @code{X} @tab
Vector Address
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{VAR} @tab Address of pending interrupt vector, read from Interrupt Vector Table
@end multitable
@regsection @code{SWIR} - Software Interrupt Register
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SWIR}
@tab @code{0} @tab
SWI interrupt mask
@end multitable
@regsection @code{EOIR} - End Of Interrupt Acknowledge Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{EOIR}
@tab @code{0} @tab
End of Interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{EOIR} @tab Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
@end multitable
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