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FMC ADC 100M 14b 4cha
Commits
d742c0b8
Commit
d742c0b8
authored
Jul 29, 2013
by
Matthieu Cattin
Browse files
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Plain Diff
hdl: Add a software reset register to reset the mezzanines related cores.
parent
2565e724
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Showing
7 changed files
with
545 additions
and
19 deletions
+545
-19
carrier_csr.tex
documentation/manuals/firmware/svec/carrier_csr.tex
+30
-0
carrier_csr.vhd
hdl/svec/rtl/carrier_csr.vhd
+31
-2
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+53
-16
svec_top_fmc_adc_100Ms.ucf
hdl/svec/svec_top_fmc_adc_100Ms.ucf
+4
-0
carrier_csr.h
hdl/svec/wb_gen/carrier_csr.h
+17
-1
carrier_csr.htm
hdl/svec/wb_gen/carrier_csr.htm
+372
-0
carrier_csr.wb
hdl/svec/wb_gen/carrier_csr.wb
+38
-0
No files found.
documentation/manuals/firmware/svec/carrier_csr.tex
View file @
d742c0b8
...
...
@@ -13,6 +13,10 @@ Status
REG @tab
@code
{
ctrl
}
@tab
Control
@item @code
{
0xc
}
@tab
REG @tab
@code
{
rst
}
@tab
Reset Register
@end multitable
@regsection @code
{
carrier
}
- Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
...
...
@@ -101,3 +105,29 @@ Reserved
@item @code
{
fp
_
leds
_
man
}
@tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@regsection @code
{
rst
}
- Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
0
}
@tab R/W @tab
@code
{
FMC0
_
N
}
@tab @code
{
0
}
@tab
State of the FMC 1 reset line
@item @code
{
1
}
@tab R/W @tab
@code
{
FMC1
_
N
}
@tab @code
{
0
}
@tab
State of the FMC 2 reset line
@item @code
{
31...2
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
fmc0
_
n
}
@tab write 0: FMC is held in reset@* write 1: Normal FMC operation
@item @code
{
fmc1
_
n
}
@tab write 0: FMC is held in reset@* write 1: Normal FMC operation
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
hdl/svec/rtl/carrier_csr.vhd
View file @
d742c0b8
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created :
Tue Jul 23 15:22:1
6 2013
-- Created :
Fri Jul 26 16:40:3
6 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -48,7 +48,13 @@ entity carrier_csr is
-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
)
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
);
-- Port for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o
:
out
std_logic
;
-- Port for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o
:
out
std_logic_vector
(
29
downto
0
)
);
end
carrier_csr
;
...
...
@@ -56,6 +62,9 @@ architecture syn of carrier_csr is
signal
carrier_csr_ctrl_fp_leds_man_int
:
std_logic_vector
(
15
downto
0
);
signal
carrier_csr_ctrl_reserved_int
:
std_logic_vector
(
15
downto
0
);
signal
carrier_csr_rst_fmc0_n_int
:
std_logic
;
signal
carrier_csr_rst_fmc1_n_int
:
std_logic
;
signal
carrier_csr_rst_reserved_int
:
std_logic_vector
(
29
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -85,6 +94,9 @@ begin
rddata_reg
<=
"00000000000000000000000000000000"
;
carrier_csr_ctrl_fp_leds_man_int
<=
"0000000000000000"
;
carrier_csr_ctrl_reserved_int
<=
"0000000000000000"
;
carrier_csr_rst_fmc0_n_int
<=
'0'
;
carrier_csr_rst_fmc1_n_int
<=
'0'
;
carrier_csr_rst_reserved_int
<=
"000000000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -125,6 +137,17 @@ begin
rddata_reg
(
31
downto
16
)
<=
carrier_csr_ctrl_reserved_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
carrier_csr_rst_fmc0_n_int
<=
wrdata_reg
(
0
);
carrier_csr_rst_fmc1_n_int
<=
wrdata_reg
(
1
);
carrier_csr_rst_reserved_int
<=
wrdata_reg
(
31
downto
2
);
end
if
;
rddata_reg
(
0
)
<=
carrier_csr_rst_fmc0_n_int
;
rddata_reg
(
1
)
<=
carrier_csr_rst_fmc1_n_int
;
rddata_reg
(
31
downto
2
)
<=
carrier_csr_rst_reserved_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -151,6 +174,12 @@ begin
carrier_csr_ctrl_fp_leds_man_o
<=
carrier_csr_ctrl_fp_leds_man_int
;
-- Reserved
carrier_csr_ctrl_reserved_o
<=
carrier_csr_ctrl_reserved_int
;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o
<=
carrier_csr_rst_fmc0_n_int
;
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o
<=
carrier_csr_rst_fmc1_n_int
;
-- Reserved
carrier_csr_rst_reserved_o
<=
carrier_csr_rst_reserved_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @
d742c0b8
...
...
@@ -272,7 +272,10 @@ architecture rtl of svec_top_fmc_adc_100Ms is
carrier_csr_stat_ddr1_cal_done_i
:
in
std_logic
;
carrier_csr_stat_reserved_i
:
in
std_logic_vector
(
26
downto
0
);
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
)
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
);
carrier_csr_rst_fmc0_n_o
:
out
std_logic
;
carrier_csr_rst_fmc1_n_o
:
out
std_logic
;
carrier_csr_rst_reserved_o
:
out
std_logic_vector
(
29
downto
0
)
);
end
component
carrier_csr
;
...
...
@@ -516,6 +519,14 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_rst_n
:
std_logic
;
signal
ddr_rst_n
:
std_logic
;
signal
sw_rst_fmc0_n
:
std_logic
;
signal
sw_rst_fmc1_n
:
std_logic
;
signal
ddr_sw_rst_fmc0_n
:
std_logic
;
signal
ddr_sw_rst_fmc1_n
:
std_logic
;
signal
fmc0_rst_n
:
std_logic
;
signal
fmc1_rst_n
:
std_logic
;
signal
fmc0_ddr_rst_n
:
std_logic
;
signal
fmc1_ddr_rst_n
:
std_logic
;
-- VME
signal
vme_data_b_out
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -702,7 +713,7 @@ begin
end
if
;
end
process
;
--
R
eset synchronisation to 125MHz system clock domain
--
System r
eset synchronisation to 125MHz system clock domain
cmp_sync_rst
:
gc_sync_ffs
port
map
(
clk_i
=>
sys_clk_125
,
...
...
@@ -711,7 +722,7 @@ begin
synced_o
=>
sys_rst_n
);
--
R
eset synchronisation to DDR clock domain
--
System r
eset synchronisation to DDR clock domain
cmp_sync_ddr_rst
:
gc_sync_ffs
port
map
(
clk_i
=>
ddr_clk
,
...
...
@@ -720,6 +731,29 @@ begin
synced_o
=>
ddr_rst_n
);
-- FMC 0 reset synchronisation to DDR clock domain
cmp_sync_fmc0_rst
:
gc_sync_ffs
port
map
(
clk_i
=>
ddr_clk
,
rst_n_i
=>
'1'
,
data_i
=>
sw_rst_fmc0_n
,
synced_o
=>
ddr_sw_rst_fmc0_n
);
-- FMC 1 reset synchronisation to DDR clock domain
cmp_sync_fmc1_rst
:
gc_sync_ffs
port
map
(
clk_i
=>
ddr_clk
,
rst_n_i
=>
'1'
,
data_i
=>
sw_rst_fmc1_n
,
synced_o
=>
ddr_sw_rst_fmc1_n
);
fmc0_rst_n
<=
sys_rst_n
and
sw_rst_fmc0_n
;
fmc1_rst_n
<=
sys_rst_n
and
sw_rst_fmc1_n
;
fmc0_ddr_rst_n
<=
ddr_rst_n
and
ddr_sw_rst_fmc0_n
;
fmc1_ddr_rst_n
<=
ddr_rst_n
and
ddr_sw_rst_fmc1_n
;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
...
...
@@ -906,7 +940,10 @@ begin
carrier_csr_stat_ddr1_cal_done_i
=>
ddr1_calib_done
,
carrier_csr_stat_reserved_i
=>
(
others
=>
'0'
),
carrier_csr_ctrl_fp_leds_man_o
=>
led_state_man
,
carrier_csr_ctrl_reserved_o
=>
open
carrier_csr_ctrl_reserved_o
=>
open
,
carrier_csr_rst_fmc0_n_o
=>
sw_rst_fmc0_n
,
carrier_csr_rst_fmc1_n_o
=>
sw_rst_fmc1_n
,
carrier_csr_rst_reserved_o
=>
open
);
-- Unused wishbone signals
...
...
@@ -991,7 +1028,7 @@ begin
)
port
map
(
sys_clk_i
=>
sys_clk_125
,
sys_rst_n_i
=>
sys
_rst_n
,
sys_rst_n_i
=>
fmc0
_rst_n
,
wb_csr_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC0_ADC
)
.
adr
,
wb_csr_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC0_ADC
)
.
dat
,
...
...
@@ -1077,7 +1114,7 @@ begin
)
port
map
(
sys_clk_i
=>
sys_clk_125
,
sys_rst_n_i
=>
sys
_rst_n
,
sys_rst_n_i
=>
fmc1
_rst_n
,
wb_csr_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC1_ADC
)
.
adr
,
wb_csr_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC1_ADC
)
.
dat
,
...
...
@@ -1165,7 +1202,7 @@ begin
g_P1_BYTE_ADDR_WIDTH
=>
30
)
port
map
(
clk_i
=>
ddr_clk
,
rst_n_i
=>
ddr_rst_n
,
rst_n_i
=>
fmc0_
ddr_rst_n
,
status_o
=>
ddr0_status
,
...
...
@@ -1251,7 +1288,7 @@ begin
p_ddr0_wb_cyc
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc0
_rst_n
=
'0'
)
then
ddr0_wb_cyc_d
<=
'0'
;
else
ddr0_wb_cyc_d
<=
cnx_master_out
(
c_WB_SLAVE_FMC0_DDR_DAT
)
.
cyc
;
...
...
@@ -1265,7 +1302,7 @@ begin
p_ddr0_addr_cnt
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc0
_rst_n
=
'0'
)
then
ddr0_addr_cnt
<=
(
others
=>
'0'
);
elsif
(
cnx_master_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
we
=
'1'
and
cnx_master_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
stb
=
'1'
and
...
...
@@ -1281,7 +1318,7 @@ begin
p_ddr0_addr_ack
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc0
_rst_n
=
'0'
)
then
cnx_master_in
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
ack
<=
'0'
;
elsif
(
cnx_master_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
stb
=
'1'
and
cnx_master_out
(
c_WB_SLAVE_FMC0_DDR_ADR
)
.
cyc
=
'1'
)
then
...
...
@@ -1318,7 +1355,7 @@ begin
g_P1_BYTE_ADDR_WIDTH
=>
30
)
port
map
(
clk_i
=>
ddr_clk
,
rst_n_i
=>
ddr_rst_n
,
rst_n_i
=>
fmc1_
ddr_rst_n
,
status_o
=>
ddr1_status
,
...
...
@@ -1404,7 +1441,7 @@ begin
p_ddr1_wb_cyc
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc1
_rst_n
=
'0'
)
then
ddr1_wb_cyc_d
<=
'0'
;
else
ddr1_wb_cyc_d
<=
cnx_master_out
(
c_WB_SLAVE_FMC1_DDR_DAT
)
.
cyc
;
...
...
@@ -1418,7 +1455,7 @@ begin
p_ddr1_addr_cnt
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc1
_rst_n
=
'0'
)
then
ddr1_addr_cnt
<=
(
others
=>
'0'
);
elsif
(
cnx_master_out
(
c_WB_SLAVE_FMC1_DDR_ADR
)
.
we
=
'1'
and
cnx_master_out
(
c_WB_SLAVE_FMC1_DDR_ADR
)
.
stb
=
'1'
and
...
...
@@ -1434,7 +1471,7 @@ begin
p_ddr1_addr_ack
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
(
sys
_rst_n
=
'0'
)
then
if
(
fmc1
_rst_n
=
'0'
)
then
cnx_master_in
(
c_WB_SLAVE_FMC1_DDR_ADR
)
.
ack
<=
'0'
;
elsif
(
cnx_master_out
(
c_WB_SLAVE_FMC1_DDR_ADR
)
.
stb
=
'1'
and
cnx_master_out
(
c_WB_SLAVE_FMC1_DDR_ADR
)
.
cyc
=
'1'
)
then
...
...
@@ -1460,7 +1497,7 @@ begin
cmp_fmc0_timetag_core
:
timetag_core
port
map
(
clk_i
=>
sys_clk_125
,
rst_n_i
=>
sys
_rst_n
,
rst_n_i
=>
fmc0
_rst_n
,
trigger_p_i
=>
trig_p
(
0
),
acq_start_p_i
=>
acq_start_p
(
0
),
...
...
@@ -1489,7 +1526,7 @@ begin
cmp_fmc1_timetag_core
:
timetag_core
port
map
(
clk_i
=>
sys_clk_125
,
rst_n_i
=>
sys
_rst_n
,
rst_n_i
=>
fmc1
_rst_n
,
trigger_p_i
=>
trig_p
(
1
),
acq_start_p_i
=>
acq_start_p
(
1
),
...
...
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @
d742c0b8
...
...
@@ -949,7 +949,11 @@ NET "ddr1_udqs_n_b" IN_TERM = NONE;
# Reset
NET "cmp_sync_ddr_rst/sync2" TIG;
NET "cmp_sync_fmc0_rst/sync2" TIG;
NET "cmp_sync_fmc1_rst/sync2" TIG;
NET "powerup_rst_n" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc0_n_int" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc1_n_int" TIG;
# DDR3
...
...
hdl/svec/wb_gen/carrier_csr.h
View file @
d742c0b8
...
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created :
Tue Jul 23 15:22:1
6 2013
* Created :
Fri Jul 26 16:40:3
6 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -88,6 +88,20 @@
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(2, 30)
#define CARRIER_CSR_RST_RESERVED_SHIFT 2
#define CARRIER_CSR_RST_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define CARRIER_CSR_RST_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
PACKED
struct
CARRIER_CSR_WB
{
/* [0x0]: REG Carrier type and PCB version */
uint32_t
CARRIER
;
...
...
@@ -95,6 +109,8 @@ PACKED struct CARRIER_CSR_WB {
uint32_t
STAT
;
/* [0x8]: REG Control */
uint32_t
CTRL
;
/* [0xc]: REG Reset Register */
uint32_t
RST
;
};
#endif
hdl/svec/wb_gen/carrier_csr.htm
View file @
d742c0b8
...
...
@@ -37,6 +37,7 @@
<span
style=
"margin-left: 20px; "
>
3.1.
<A
href=
"#sect_3_1"
>
Carrier type and PCB version
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
Status
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
Control
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.4.
<A
href=
"#sect_3_4"
>
Reset Register
</a></span><br/>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
...
...
@@ -107,6 +108,23 @@ carrier_csr_ctrl
CTRL
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x3
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#RST"
>
Reset Register
</a>
</td>
<td
class=
"td_code"
>
carrier_csr_rst
</td>
<td
class=
"td_code"
>
RST
</td>
</tr>
</table>
<h3><a
name=
"sect_2_0"
>
2. HDL symbol
</a></h3>
...
...
@@ -383,6 +401,91 @@ carrier_csr_ctrl_reserved_o[15:0]
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Reset Register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc0_n_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc1_n_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_reserved_o[29:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
</table>
<h3><a
name=
"sect_3_0"
>
3. Register description
</a></h3>
...
...
@@ -1192,6 +1295,275 @@ RESERVED
</b>
[
<i>
read/write
</i>
]: Reserved
<br>
Ignore on read, write with 0's
</ul>
<a
name=
"RST"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Reset Register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
carrier_csr_rst
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x3
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
RST
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0xc
</td>
</tr>
</table>
<p>
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[29:22]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[21:14]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[13:6]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
6
class=
"td_field"
>
RESERVED[5:0]
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
FMC1_N
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
FMC0_N
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_N
</b>
[
<i>
read/write
</i>
]: State of the FMC 1 reset line
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
<li><b>
FMC1_N
</b>
[
<i>
read/write
</i>
]: State of the FMC 2 reset line
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
<li><b>
RESERVED
</b>
[
<i>
read/write
</i>
]: Reserved
<br>
Ignore on read, write with 0's
</ul>
...
...
hdl/svec/wb_gen/carrier_csr.wb
View file @
d742c0b8
...
...
@@ -125,4 +125,42 @@ peripheral {
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanines including the ddr interface and the time-tagging core.";
field {
name = "State of the FMC 1 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation";
type = BIT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation";
type = BIT;
size = 1;
prefix = "fmc1_n";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
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