Review02032010
h1. Design review of FMCADC100M14b4cha
schematics version of 2010-02-26 16:29.16
Present
Michael Sordet (BE/BI), Matthieu Cattin, Pablo Alvarez, Erik van der Bij, Maciej Fimiarz (designer)
Review
h2. General
Maciej gave a general overview of the design. It is optmised for noise levels, that's why low value resistors are used and the input impedance is only 1 KOhm (or 50 Ohm selectable). The stability of the gain and offset is mainly influenced by the MOS switches.
The anti-aliasing filter has it's -3dB point at 25 MHz, with a 4-pole filter. The sampling frequency is programmable on the local oscillator, or can be coming from the FMC carrier (production option), but it is supposed to be 100 MHz.
The lowest sensitivity setting of the ADC (/- 1V) is used for noise reasons. But for this the differential ampifier in front should amplify by a factor 2. It is not clear if this is better than having the highest sensitivity setting of the ADC (/- 0.5V) and have a unity gain amplification in front.
Detailed comments
Sheet 1: High Pin Count Connector
- LA00_CC_P should be called LA00_P_CC (same for N). Change also where this signal is used.
- VIO_B_M2C is not used: remove signal
- to prevent confusion: remove all signals that are not used in the design
- Mark the meaning of B1-B4 and FIG1-FIG6
Sheet 2: Input stage
- consider inserting an inductor at the negative input to make it symmetrical to the positive input (verify AA's mail about this).
- Put a note on the input ranges, voltage ranges at critical points in the schematic.
- Add 2 resistors to select the sensitivity of the ADC (SENSE)
Sheet
Additions to the manual
- Add a note about the crosstalk: do not put an input with a /-5V range next to one with a/-50mV range.
PCB layout (prelinary review)
- consider placing the filter inductors alternatively on the top and bottom side to reduce coupling.