This design study proposes two different architectures for the implementation of a two-channel,
8bit, 1GSPS ADC on an FMC board. One is based on two single-channel ADCs from Analog Devices (ADI)
using a parallel LVDS interface for their readout by the FPGA of the FMC carrier, while the other
one is based on a dual-channel ADC from Texas Instruments (TI) with a JESD204B interface coupled to
a local FPGA on the FMC (and, optionally, some external memory, also on the FMC).
The reason for putting an extra FPGA (and, optionally, external memory) on the FMC is that our FMC
carriers use an LPC connector which does not provide enough high-speed signal pairs to be able to
pass JESD204B through it. Therefore, a local FPGA takes care of ADC readout and then it makes the
data available to the carrier FPGA via some pre-agreed interface between the two. This implies of
course that, since there is not enough bandwidth to stream the data to the carrier FPGA, the FMC
FPGA must perform the full acquisition, store it and then pass it on to the carrier FPGA at a slower
rate. Hence the need to have an external memory on the FMC in the second scenario, in order to be able
to store more samples than what is possible with just the FMC FPGA block RAMs.
Despite the fact that the JESD204B is a very attractive interface for the readout of high-speed
ADCs, CERN has decided to go for the parallel LVDS solution. The following is the list of arguments
that justify this decision (in random order).
Licensing issues with the JESD204B core
Xilinx, Intel/Altera and Microchip/Microsemi, each provide their own, proprietary JESD204B IP
core. In the case of Xilinx and Intel, the core is available for a fee, with a one-year license. In
the case of Microchip, the core is available at no extra cost if one has already bought a Libero
license. In all these cases, it would be impossible to distribute the full design in OHWR under an
Another alternative could be the
ADI JESD204 core from Analog
Devices, which is available under a GPL2 license. However, CERN does not think that GPL2 is a fully
satisfactory reciprocal licence for HDL, for reasons explained in the following links:
One final alternative would be to develop our own JESD204 IP core, but, given the complexity of the
interface, this is not something that could be ready to be used in the context of the development of
Sample memory considerations
One important requirement for CERN is the ability to be able to store enough samples to represent
several milliseconds worth of data. This is due to the nature of some of the signals that need to be
observed, but also due to WRTD, which can introduce several hundreds of microseconds of delay to the trigger signals.
In the case of the parallel LVDS interface, the FMC carrier has enough of external memory to cover
this requirement. In the case of the JESD204B interface, the FMC FPGA does not have enough block
RAM, which makes it necessary to also add an external memory to the FMC. This in turn has cost,
design complexity and signal integrity implications.
Having two FPGAs of course makes the system more complex to design and to maintain. Also, from the
software/drivers point of view, one needs to always take care of the two FPGAs, make sure that all
gateware/firmware/software versions are compatible etc.
Another important consideration is that due to WRTD, the
FPGA that implements the triggering logic needs to be fully aware of White Rabbit.
This means to have access to WR time, but also to WR data
(to be able to send/receive triggers over WR). All the necessary circuitry for WR exists on
the FMC carrier board (SFP, DACs, VCXOs, etc), together with the WR PTP core itself. In the case of
the JESD204B interface, since all triggering will be performed by the FMC FPGA, this means that we
will have to somehow provide full access to WR to the FMC FPGA, from the carrier FPGA, while making
sure that we do not deteriorate the performance of WR and WRTD (in terms of accuracy and latency).
Last but not least, the available area on an FMC card is quite limited. Placing an FPGA and
external memory (along with supporting circuitry, such as power supplies) together with the analog
front-end on a single FMC card can be very challenging.
Placing high-speed digital circuits with high pin-counts like the FPGA and external memory on the
FMC will introduce a non-negligible challenge to the circuit designer in terms of maintaining the
signal integrity of the analog front-end. This will be further accentuated by the limited area of
the FMC. We strongly prefer a simpler design with better signal integrity.
The cost of a single-channel ADI ADC is 55EUR, leading to 110EUR for the two channels, while the
cost for the TI ADC is 800EUR. Although both Sundance and CERN have received assurances from TI that
they can offer us significant discounts, even a 60% discount would still make it three times more
expensive. This is of course normal, since it is a much better performance device than the ADI one,
but the ADI already covers the required specifications for this project.
Once the JESD204B ADC has been accounted for (even with a heavy discount), one needs to also
consider the price of the FMC FPGA (and external memory). An MPF300T Polaris FPGA as suggested in
the design study is another 300EUR. Furthermore, with an FPGA and external memories on the FMC, both
using BGA packages, one can also expect more layers and lower tolerances for the PCB production.