The following features should be controllable by software:
Input signal range, coupling, termination and offset adjustment
Sampling clock selection
Direction of external trigger in/out
ADC configuration and status
The offset adjustment must not clip the signal at the highest range
(+/- 5V). That is why the "max input signal amplitude" has been
specified as 10V, even though the selection of signal ranges only
goes up to 5V. This way, a +10V pulse with -5V offset could still be
digitised without clipping.
The sampling clock should be derived from a voltage-controllable
125MHz clock source, controlled via an SPI DAC.
A copy of the 125MHz clock source should be available on the FMC