FMC ADC 1G 8b 2cha
Project description
The FmcAdc1G182cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.
The project is currently in the planning phase.
Preliminary Specifications
Parameter | Value |
PCB format | VITA 57.1 FMC LPC |
Connectors | SMA |
Sampling Rate | 1 GSPS (preferably 2GSPS) |
Input Signal Type | single-ended |
Resolution | 8 bits |
Number of Channels | 2 (preferably 4) |
Bandwidth (-3dB) | 50Ω: DC to 400MHz (or better) |
1MΩ: DC to 300MHz (or better) | |
Input Signal Coupling and Termination | AC (8 Hz LF limit, after 50 Ω termination) |
DC-50Ω | |
DC-1MΩ | |
Input Signal Range | +/- 50mV |
+/- 250mV | |
+/- 500mV | |
+/- 2.5V | |
+/- 5V | |
Max Input Signal Amplitude | +/- 10V |
SNR | > 40dB full bandwidth over all input ranges |
ENOB | > 6.5 full bandwidth over all input ranges |
Offset Adjustment Range | +/- 5V |
Offset Adjustment Resolution | 16 bits |
Offset Adjustment Accuracy | < 1% |
Additional I/O | External TTL trigger in/out (bidirectional) |
External 10MHz clock input | |
Self-calibration | Automatic zeroing of offset and gain |
ADC interface | serial/parallel LVDS |
Temperature sensor | via one-wire ds182x |
FMC EEPROM | 24C02, as per VITA 57.1 |
Power Consumption | < 7W |
Notes:*
- The following features should be controllable by software:
- Input signal range, coupling, termination and offset adjustment
- Self-calibration
- Sampling clock selection
- Direction of external trigger in/out
- ADC configuration and status
- The offset adjustment must not clip the signal at the highest range (+/- 5V). That is why the "max input signal amplitude" has been specified as 10V, even though the selection of signal ranges only goes up to 5V. This way, a +10V pulse with -5V offset could still be digitised without clipping.
- The sampling clock should be derived from a voltage-controllable 125MHz clock source, controlled via an SPI DAC.
- A copy of the 125MHz clock source should be available on the FMC connector pins.
Project information
- Preliminary study
-
1 GSPS digitizer based on the FPGA Mezzanine Card (FMC) standard
with low-count pin connector,
M.Vasilyev, August 2015
- Summer student work, design study. Other input ranges, one-channel.
Contacts
Technical questions
- Dimitris Lampridis - CERN
General questions about project
- Erik van der Bij - CERN
Status
Date | Event |
03-08-2011 | Start of project. |
14-09-2011 | Preliminary study of an ADC mezzanine, 1 GSps, 10bits, 2 channels published |
30-09-2011 | Project on hold. Not resourced. |
20-11-2013 | A company is interested in designing this card, but development cost may be a problem. Are you interested? Contact Erik |
22-08-2015 | Summer student made a design study. |
13-04-2018 | Renewed discussion about 1 GSPS ADC for OASIS. |
12-11-2018 | Preliminary Specifications updated. |
Erik van der Bij / Dimitris Lampridis - November 2018