UNDER CONSTRUCTION...
Project description
The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). It was designed within the framework of the WR-D3S-ADC project to bandpass sampling signals with a carrier frequency higher than 125 MHz, but BW of only a few MHz. The design was based on the fmc-adc-100m14b4cha, but 2 main changes were applied:
- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order
to increase the sampling frequency to 125MHz and synchronize it using
the WR clock.
- and the input acquisition circuitry of every adc chanel was
simplified and replaced by RF transformers as recommended into the ADC
datasheet.
Specifications
Parameter | Value |
max. sample rate | 125 MSPS |
analog bandwidth | 3 MHz. AC-coupled |
bits/sample | 14 bit |
channels | 4 |
connectors | 4 x LEMO 00 for signals, 1 x LEMO 00 for trigger |
input impedance | 50 Ohm |
FMC to carrier interface | FMC high pin count connector (HPC only used if external clock is selected) |
Clock source | Internal: from programmable on-board oscillator. External: from dedicated FMC connector pins (HPC) when changing two capacitors. |
Releases
- Hardware: see EDMS (CERN Electronic Document Management System) document EDA-03502-V1-0 v.0.
Contacts
- Eva Calvo - CERN
General question about project
- Erik van der Bij - CERN
Status
Date | Event |
19-10-2016 | Layout being finalized. |
15-11-2016 | Manufacturing of 3 assembled boards finished |
21-11-2016 | Initial test of the 3 assembled boards finished |
08-12-2016 | Front panels received. |
Eva Calvo - 12 December 2016