Project description
fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). It is designed for undersampling signals with a frequency higher than 125 MHz. The design is based on the fmc-adc-100m14b4cha.
TEMPLATE - NEEDS UPDATING*
The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. By default it uses only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: /-50mV,/-0.5V, /-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of/- 5V that is independent on the chosen gain range.
Please refer to the corresponding sub-project for detailed information.
Specifications
Parameter | Value |
max. sample rate | 105 MSPS (default 100MSPS) |
analog bandwidth | 30 MHz. DC-coupled (40 MHz possible by changing eight capacitors) |
bits/sample | 14 bit |
ENOB | 11, 11.5, 11.7 bit (@ /-50mV,/-0.5V, +/-5V range) |
channels | 4 |
connectors | 4 x LEMO 00 for signals, 1 x LEMO 00 for trigger |
input impedance | 1 kOhm / 50 Ohm - software selectable |
gain steps | +/-50 mV +/-0.5 V +/-5 V |
offset correction range | +/- 5 V for every input voltage range |
max. gain error | +/- 1 % |
SNR | 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) |
FMC to carrier interface | FMC high pin count connector (HPC only used if external clock is selected) |
Clock source | Internal: from programmable on-board oscillator. External: from dedicated FMC connector pins (HPC) when changing two capacitors. |
Releases
- Hardware: see EDMS (CERN Electronic Document Management System) document EDA-02063.
- Gateware: see gateware sub-project releases page.
- Software: see software sub-project releases page.
Project Information
- Users
- Frequently Asked Questions
- Mailing list fmc-adc-100m14b4cha@ohwr.org and its archive.
Contacts
Commercial producers
- 4ch 105 Msps 14 bit ADC 30 MHz INCAA Computers, Netherlands. (standard design)
- 4ch 105 Msps 14 bit ADC 40 MHz INCAA Computers, Netherlands.
- FMC ADC 100M 14b 4cha Creotech, Poland
General question about project
- Erik van der Bij - CERN
Status
Date | Event |
19-10-2016 | Layout being finalized. |
Eva Calvo - 19 October 2016