FMC DAC 250MSPS 16b 4CH
Project description
The FMC DAC 250MSPS 16b 4CH is a single width mezzanine card (69 x 76.5mm) which has been specifically designed to be plugged on a carrier card VXS DSP FMC Carrier but other carriers can also be freely used. The mezzanine card is designed according to a VITA57.1 FPGA Mezzanine Card (FMC) standard which sets the specifications for the electromechanical aspects of the mezzanine card.
The FMC-DAC-4CH-16b-250MSPS card receives digital data input from a FPGA. This data is sampled with four digital-to-analog converters which provide four identical analog outputs. These outputs are amplified, filtered with a 40MHz cutoff frequency and four RF-signal outputs of max. 7.6Vpp are provided by the mezzanine card. The 7.6Vpp voltage is the saturation point of the driving amplifier. In addition, the board has a Serial Peripheral Interface (SPI) for D/A-converter and A/D-converter control; an Inter-Integrated Circuit (I2C) bus which connects devices such as a voltage/temperature monitoring chip, a 64-bit identification number chip, I2C-to-1-wire bridge, an EEPROM memory and a front panel LED controller chip.
The mezzanine card is using a High Pin Count (HPC) connector which provides up to 400 pins from which 160 are used definable. The stack height of the connector is 8.5mm.
Hardware images
Front panel of the mezzanine card*
Top and bottom images of the version 2 are coming soon...
Block diagrams
Main features
- Output
- 4 identical channels
- each 50 ohm series terminated with SMC connectors in the output, 8.5mm front panel covering the output
- Bit resolution
- 16 bit
- Peak maximum output Upp
- 7.6Vpp DC-coupled, saturation point
- Output scaling factor Upp/8
- 18dB attenuator DC-coupled, selected with a switch
- Analog Bandwidth
- 40 MHz
- DAC sampling frequency
- 250 MSPS, tested up to 125 MSPS
- Clock source
- 2 differential external clock lines which are distributed via FMC connector nom. 125 MSPS
- Signaling standards
- LVCMOS33 for input data, LVTTL33 for some of the I/O control signals and LVPECL/LVDS for the differential input clock signals
- Interface between mezzanine and carrier
- VITA 57 FMC High Pin Count 400-pin connector, FMC connector stack height 8.5mm
- Standard for the daughter card
- FMC standard (VITA 57) which specifies the electrical and mechanical aspects
Project information
- Official production information EDMS EDA-02069
Releases
"Hardware"
Contacts
General questions about the project
- Petri Leinonen - CERN-BE-RF-FB
Status
Date | Event |
June 2009 | Project planning starts |
Petri Leinonen - 19th of May 2012