FMC DAC 600M 12b 1cha DDS
Project description
The FMC DAC 600M 12b 1cha DDS board can be used to distribute RF signals
over the White
Rabbit network.
The idea of RF distribution over WR is described in the Distributed
Direct Digital Synthesis over White Rabbit (D3S)
project.
Together with the Simple PCIe FMC Carrier - SPEC this board makes a complete WR RF distribution node.
FMC DDS prototype board (version 0)* (Block diagram showing possible
use)
Main Features
- Low-Pin Count FMC
- I/Os (LEMO 00):
- 50 Ohm RF reference in (up to 500 MHz)
- 50 Ohm RF monitor/synthesis out (up to 500 MHz)
- Jitter < 20ps RMS (V2-1 design). (Goal < 2ps RMS (V3?))
- Divided beam clock output (LVTTL)
- External Trigger input (LVTTL)
- Fine-delay adjusted RF synchronous trigger output (LVTTL)
- 14-bit 600MHz DAC (MAX5890EGK+D) with splitter and amplifier
- ADF4002 phase detector + programmable LPF + 16-bit ADC
- AD9510 PLL with external oscillator for jitter cleaning of the synthesized RF signal
- Clocking resources
- 1x user-specified frequency VCTCXO controlled by the AD9510 PLL for low additional jitter cleaning
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- Low-jitter frequency synthesizer/fanout (AD9516)
- Trigger output (beam-clock synchronous) with fine delay adjustment by SY89295
- Miscellaneous
- On-board thermometer IC (DS18B20U+)
- 64kbit EEPROM (24AA64T-I/MC) connected for storing application parameters
- 2 LEDs
- 4-layer PCB
Project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03010
- Block diagram showing possible use
- Users
- Frequently Asked Questions
Related projects
Contacts
Commercial producers
- Creotech, Poland
General question about project
- Tomasz Włostowski - CERN
Status
Date | Event |
01-04-2013 | Specification written. |
24-04-2013 | Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL). |
08-05-2013 | Proof-of-concept VHDL and software. |
20-11-2013 | Specification of new version (v2) of the board including functionality of pulse generation with <50 ps RMS jitter and programmable fine delay. |
22-11-2013 | LNLS put order for the v2 design. |
29-12-2013 | Schematics of v2 at repository - ready for review. |
20-01-2014 | Reviewed schematics of v2: Review-jan-2014. |
24-09-2014 | V2 Design released in EDMS. |
15-01-2015 | 4 EDA-03010-V1-0 cards built and powered (order). |
24-08-2015 | Production test system written. Not yet tested. |
29-09-2015 | PTS not yet tested. Some components need to be changed. Spurs on phase noise need investigation. |
30-09-2015 | Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type). |
04-04-2016 | 5 EDA-03010-V1-0 cards with modifications built and received (order). |
09-07-2018 | Opening up project to investigate RF timing distribution over WR. |
9 July 2018