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-- Title          : Wishbone slave core for DDS RF distribution WB Slave
---------------------------------------------------------------------------------------
-- File           : /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- Created        : Tue Feb  2 09:40:18 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

package dds_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_dds_in_registers is record
    cr_wr_link_i                             : std_logic;
    cr_wr_time_i                             : std_logic;
    gpior_pll_sys_ld_i                       : std_logic;
    gpior_pll_sdio_i                         : std_logic;
    gpior_pll_vcxo_status_n_i                : std_logic;
    gpior_pll_vcxo_sdo_i                     : std_logic;
    gpior_adf_ld_i                           : std_logic;
    gpior_adc_sdo_i                          : std_logic;
    gpior_fmc_present_i                      : std_logic;
    gpior_test_pll_ld_i                      : std_logic;
    pd_fifo_wr_req_i                         : std_logic;
    pd_fifo_data_i                           : std_logic_vector(15 downto 0);
    tune_fifo_rd_req_i                       : std_logic;
    i2cr_scl_in_i                            : std_logic;
    i2cr_sda_in_i                            : std_logic;
    hit_cnt_hit_cnt_i                        : std_logic_vector(23 downto 0);
    miss_cnt_miss_cnt_i                      : std_logic_vector(23 downto 0);
    rx_cnt_rx_cnt_i                          : std_logic_vector(23 downto 0);
    tx_cnt_tx_cnt_i                          : std_logic_vector(23 downto 0);
    pll_ld_i                                 : std_logic;
    pi_wr_req_i                              : std_logic;
    pi_data_i                                : std_logic_vector(15 downto 0);
    gw_id_i                                  : std_logic_vector(31 downto 0);
    fpgactrl_mainpll_i                       : std_logic;
    fpgapll_clk2_stat_lock_i                 : std_logic;
    clk0_freq_i                              : std_logic_vector(31 downto 0);
    clk1_freq_i                              : std_logic_vector(31 downto 0);
    clk2_freq_i                              : std_logic_vector(31 downto 0);
    pdtest_period_i                          : std_logic_vector(15 downto 0);
    delphase_stable_i                        : std_logic;
    delphase_value_i                         : std_logic;
    trigger_freq_i                           : std_logic_vector(31 downto 0);
    end record;
  
  constant c_dds_in_registers_init_value: t_dds_in_registers := (
    cr_wr_link_i => '0',
    cr_wr_time_i => '0',
    gpior_pll_sys_ld_i => '0',
    gpior_pll_sdio_i => '0',
    gpior_pll_vcxo_status_n_i => '0',
    gpior_pll_vcxo_sdo_i => '0',
    gpior_adf_ld_i => '0',
    gpior_adc_sdo_i => '0',
    gpior_fmc_present_i => '0',
    gpior_test_pll_ld_i => '0',
    pd_fifo_wr_req_i => '0',
    pd_fifo_data_i => (others => '0'),
    tune_fifo_rd_req_i => '0',
    i2cr_scl_in_i => '0',
    i2cr_sda_in_i => '0',
    hit_cnt_hit_cnt_i => (others => '0'),
    miss_cnt_miss_cnt_i => (others => '0'),
    rx_cnt_rx_cnt_i => (others => '0'),
    tx_cnt_tx_cnt_i => (others => '0'),
    pll_ld_i => '0',
    pi_wr_req_i => '0',
    pi_data_i => (others => '0'),
    gw_id_i => (others => '0'),
    fpgactrl_mainpll_i => '0',
    fpgapll_clk2_stat_lock_i => '0',
    clk0_freq_i => (others => '0'),
    clk1_freq_i => (others => '0'),
    clk2_freq_i => (others => '0'),
    pdtest_period_i => (others => '0'),
    delphase_stable_i => '0',
    delphase_value_i => '0',
    trigger_freq_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_dds_out_registers is record
      cr_test_o                                : std_logic;
      cr_slave_o                               : std_logic;
      cr_master_o                              : std_logic;
      cr_adc_bb_enable_o                       : std_logic;
      cr_clk_id_o                              : std_logic_vector(15 downto 0);
      gpior_pll_sys_cs_n_o                     : std_logic;
      gpior_pll_sys_reset_n_o                  : std_logic;
      gpior_pll_sys_sync_n_o                   : std_logic;
      gpior_pll_sclk_o                         : std_logic;
      gpior_pll_sdio_o                         : std_logic;
      gpior_pll_sdio_load_o                    : std_logic;
      gpior_pll_sdio_dir_o                     : std_logic;
      gpior_pll_vcxo_cs_n_o                    : std_logic;
      gpior_pll_vcxo_function_o                : std_logic;
      gpior_adf_ce_o                           : std_logic;
      gpior_adf_clk_o                          : std_logic;
      gpior_adf_le_o                           : std_logic;
      gpior_adf_data_o                         : std_logic;
      gpior_adc_sdi_o                          : std_logic;
      gpior_adc_cnv_o                          : std_logic;
      gpior_adc_sck_o                          : std_logic;
      pd_fifo_wr_full_o                        : std_logic;
      pd_fifo_wr_empty_o                       : std_logic;
      tune_fifo_rd_empty_o                     : std_logic;
      tune_fifo_data_o                         : std_logic_vector(31 downto 0);
      freq_hi_o                                : std_logic_vector(31 downto 0);
      freq_lo_o                                : std_logic_vector(31 downto 0);
      gain_o                                   : std_logic_vector(15 downto 0);
      rstr_pll_rst_o                           : std_logic;
      rstr_sw_rst_o                            : std_logic;
      rstr_freq_res_o                          : std_logic;
      i2cr_scl_out_o                           : std_logic;
      i2cr_sda_out_o                           : std_logic;
      pir_kp_o                                 : std_logic_vector(15 downto 0);
      pir_ki_o                                 : std_logic_vector(15 downto 0);
      dlyr_delay_o                             : std_logic_vector(15 downto 0);
      phaser_phase_o                           : std_logic_vector(15 downto 0);
      macl_macl_o                              : std_logic_vector(31 downto 0);
      mach_mach_o                              : std_logic_vector(15 downto 0);
      pi_wr_full_o                             : std_logic;
      pi_wr_empty_o                            : std_logic;
      dac_ampl_o                               : std_logic_vector(13 downto 0);
      dac_en_o                                 : std_logic;
      dac_type_o                               : std_logic_vector(1 downto 0);
      test_comm_reg_o                          : std_logic_vector(15 downto 0);
      test_comm_led_r_o                        : std_logic;
      test_comm_led_g_o                        : std_logic;
      fpgapll_clk2_ctrl_rst_o                  : std_logic;
      oscdac_data_o                            : std_logic_vector(15 downto 0);
      oscdac_load_o                            : std_logic;
      adcinterface_source_o                    : std_logic;
      adcinterface_trigger_o                   : std_logic;
      delay_value_o                            : std_logic_vector(9 downto 0);
      delay_enable_o                           : std_logic;
      delay_load_o                             : std_logic;
      delay_maxval_o                           : std_logic_vector(15 downto 0);
      end record;
    
    constant c_dds_out_registers_init_value: t_dds_out_registers := (
      cr_test_o => '0',
      cr_slave_o => '0',
      cr_master_o => '0',
      cr_adc_bb_enable_o => '0',
      cr_clk_id_o => (others => '0'),
      gpior_pll_sys_cs_n_o => '0',
      gpior_pll_sys_reset_n_o => '0',
      gpior_pll_sys_sync_n_o => '0',
      gpior_pll_sclk_o => '0',
      gpior_pll_sdio_o => '0',
      gpior_pll_sdio_load_o => '0',
      gpior_pll_sdio_dir_o => '0',
      gpior_pll_vcxo_cs_n_o => '0',
      gpior_pll_vcxo_function_o => '0',
      gpior_adf_ce_o => '0',
      gpior_adf_clk_o => '0',
      gpior_adf_le_o => '0',
      gpior_adf_data_o => '0',
      gpior_adc_sdi_o => '0',
      gpior_adc_cnv_o => '0',
      gpior_adc_sck_o => '0',
      pd_fifo_wr_full_o => '0',
      pd_fifo_wr_empty_o => '0',
      tune_fifo_rd_empty_o => '0',
      tune_fifo_data_o => (others => '0'),
      freq_hi_o => (others => '0'),
      freq_lo_o => (others => '0'),
      gain_o => (others => '0'),
      rstr_pll_rst_o => '0',
      rstr_sw_rst_o => '0',
      rstr_freq_res_o => '0',
      i2cr_scl_out_o => '0',
      i2cr_sda_out_o => '0',
      pir_kp_o => (others => '0'),
      pir_ki_o => (others => '0'),
      dlyr_delay_o => (others => '0'),
      phaser_phase_o => (others => '0'),
      macl_macl_o => (others => '0'),
      mach_mach_o => (others => '0'),
      pi_wr_full_o => '0',
      pi_wr_empty_o => '0',
      dac_ampl_o => (others => '0'),
      dac_en_o => '0',
      dac_type_o => (others => '0'),
      test_comm_reg_o => (others => '0'),
      test_comm_led_r_o => '0',
      test_comm_led_g_o => '0',
      fpgapll_clk2_ctrl_rst_o => '0',
      oscdac_data_o => (others => '0'),
      oscdac_load_o => '0',
      adcinterface_source_o => '0',
      adcinterface_trigger_o => '0',
      delay_value_o => (others => '0'),
      delay_enable_o => '0',
      delay_load_o => '0',
      delay_maxval_o => (others => '0')
      );
    function "or" (left, right: t_dds_in_registers) return t_dds_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body dds_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers is
variable tmp: t_dds_in_registers;
begin
tmp.cr_wr_link_i := f_x_to_zero(left.cr_wr_link_i) or f_x_to_zero(right.cr_wr_link_i);
tmp.cr_wr_time_i := f_x_to_zero(left.cr_wr_time_i) or f_x_to_zero(right.cr_wr_time_i);
tmp.gpior_pll_sys_ld_i := f_x_to_zero(left.gpior_pll_sys_ld_i) or f_x_to_zero(right.gpior_pll_sys_ld_i);
tmp.gpior_pll_sdio_i := f_x_to_zero(left.gpior_pll_sdio_i) or f_x_to_zero(right.gpior_pll_sdio_i);
tmp.gpior_pll_vcxo_status_n_i := f_x_to_zero(left.gpior_pll_vcxo_status_n_i) or f_x_to_zero(right.gpior_pll_vcxo_status_n_i);
tmp.gpior_pll_vcxo_sdo_i := f_x_to_zero(left.gpior_pll_vcxo_sdo_i) or f_x_to_zero(right.gpior_pll_vcxo_sdo_i);
tmp.gpior_adf_ld_i := f_x_to_zero(left.gpior_adf_ld_i) or f_x_to_zero(right.gpior_adf_ld_i);
tmp.gpior_adc_sdo_i := f_x_to_zero(left.gpior_adc_sdo_i) or f_x_to_zero(right.gpior_adc_sdo_i);
tmp.gpior_fmc_present_i := f_x_to_zero(left.gpior_fmc_present_i) or f_x_to_zero(right.gpior_fmc_present_i);
tmp.gpior_test_pll_ld_i := f_x_to_zero(left.gpior_test_pll_ld_i) or f_x_to_zero(right.gpior_test_pll_ld_i);
tmp.pd_fifo_wr_req_i := f_x_to_zero(left.pd_fifo_wr_req_i) or f_x_to_zero(right.pd_fifo_wr_req_i);
tmp.pd_fifo_data_i := f_x_to_zero(left.pd_fifo_data_i) or f_x_to_zero(right.pd_fifo_data_i);
tmp.tune_fifo_rd_req_i := f_x_to_zero(left.tune_fifo_rd_req_i) or f_x_to_zero(right.tune_fifo_rd_req_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.hit_cnt_hit_cnt_i := f_x_to_zero(left.hit_cnt_hit_cnt_i) or f_x_to_zero(right.hit_cnt_hit_cnt_i);
tmp.miss_cnt_miss_cnt_i := f_x_to_zero(left.miss_cnt_miss_cnt_i) or f_x_to_zero(right.miss_cnt_miss_cnt_i);
tmp.rx_cnt_rx_cnt_i := f_x_to_zero(left.rx_cnt_rx_cnt_i) or f_x_to_zero(right.rx_cnt_rx_cnt_i);
tmp.tx_cnt_tx_cnt_i := f_x_to_zero(left.tx_cnt_tx_cnt_i) or f_x_to_zero(right.tx_cnt_tx_cnt_i);
tmp.pll_ld_i := f_x_to_zero(left.pll_ld_i) or f_x_to_zero(right.pll_ld_i);
tmp.pi_wr_req_i := f_x_to_zero(left.pi_wr_req_i) or f_x_to_zero(right.pi_wr_req_i);
tmp.pi_data_i := f_x_to_zero(left.pi_data_i) or f_x_to_zero(right.pi_data_i);
tmp.gw_id_i := f_x_to_zero(left.gw_id_i) or f_x_to_zero(right.gw_id_i);
tmp.fpgactrl_mainpll_i := f_x_to_zero(left.fpgactrl_mainpll_i) or f_x_to_zero(right.fpgactrl_mainpll_i);
tmp.fpgapll_clk2_stat_lock_i := f_x_to_zero(left.fpgapll_clk2_stat_lock_i) or f_x_to_zero(right.fpgapll_clk2_stat_lock_i);
tmp.clk0_freq_i := f_x_to_zero(left.clk0_freq_i) or f_x_to_zero(right.clk0_freq_i);
tmp.clk1_freq_i := f_x_to_zero(left.clk1_freq_i) or f_x_to_zero(right.clk1_freq_i);
tmp.clk2_freq_i := f_x_to_zero(left.clk2_freq_i) or f_x_to_zero(right.clk2_freq_i);
tmp.pdtest_period_i := f_x_to_zero(left.pdtest_period_i) or f_x_to_zero(right.pdtest_period_i);
tmp.delphase_stable_i := f_x_to_zero(left.delphase_stable_i) or f_x_to_zero(right.delphase_stable_i);
tmp.delphase_value_i := f_x_to_zero(left.delphase_value_i) or f_x_to_zero(right.delphase_value_i);
tmp.trigger_freq_i := f_x_to_zero(left.trigger_freq_i) or f_x_to_zero(right.trigger_freq_i);
return tmp;
end function;
end package body;
