def WBGEN2_GEN_MASK(offset, size):
	return (((1<<(size))-1) << (offset))
def WBGEN2_GEN_WRITE(value, offset, size):
	return (((value) & ((1<<(size))-1)) << (offset))
def WBGEN2_GEN_READ(reg, offset, size):
	return (((reg) >> (offset)) & ((1<<(size))-1))




def wbset(current, mask): 
	current |= mask;
	return current;

def wbclear(current, mask):
	current &= ~mask;
	return current;

def wbsetval(current, mask, val):
	return wbset(current, mask) if val else wbclear(current, mask)

DDS_REG_CR = 0x00000000
DDS_REG_GPIOR = 0x00000004
DDS_REG_FREQ_HI = 0x00000008
DDS_REG_FREQ_LO = 0x0000000c
DDS_REG_GAIN = 0x00000010
DDS_REG_RSTR = 0x00000014
DDS_REG_I2CR = 0x00000018
DDS_REG_PIR = 0x0000001c
DDS_REG_DLYR = 0x00000020
DDS_REG_PHASER = 0x00000024
DDS_REG_MACL = 0x00000028
DDS_REG_MACH = 0x0000002c
DDS_REG_HIT_CNT = 0x00000030
DDS_REG_MISS_CNT = 0x00000034
DDS_REG_RX_CNT = 0x00000038
DDS_REG_TX_CNT = 0x0000003c
DDS_REG_PLL = 0x00000040
DDS_REG_GW = 0x00000044
DDS_REG_DAC = 0x00000048
DDS_REG_TEST_COMM = 0x0000004c
DDS_REG_FPGACTRL = 0x00000050
DDS_REG_FPGAPLL_CLK2_CTRL = 0x00000054
DDS_REG_FPGAPLL_CLK2_STAT = 0x00000058
DDS_REG_CLK0 = 0x0000005c
DDS_REG_CLK1 = 0x00000060
DDS_REG_CLK2 = 0x00000064
DDS_REG_PDTEST = 0x00000068
DDS_REG_OSCDAC = 0x0000006c
DDS_REG_ADCINTERFACE = 0x00000070
DDS_REG_DELAY = 0x00000074
DDS_REG_DELPHASE = 0x00000078
DDS_REG_TRIGGER = 0x0000007c
DDS_REG_PD_FIFO_R0 = 0x00000080
DDS_REG_PD_FIFO_CSR = 0x00000084
DDS_REG_TUNE_FIFO_R0 = 0x00000088
DDS_REG_TUNE_FIFO_CSR = 0x0000008c
DDS_REG_PI_R0 = 0x00000090
DDS_REG_PI_CSR = 0x00000094



def DDS_CR_TEST():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_CR_SLAVE():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_CR_MASTER():
	return WBGEN2_GEN_MASK(2, 1)
def DDS_CR_ADC_BB_ENABLE():
	return WBGEN2_GEN_MASK(3, 1)
def DDS_CR_WR_LINK():
	return WBGEN2_GEN_MASK(4, 1)
def DDS_CR_WR_TIME():
	return WBGEN2_GEN_MASK(5, 1)
def DDS_CR_CLK_ID_MASK():
	return WBGEN2_GEN_MASK(16, 16)
def DDS_GPIOR_PLL_SYS_CS_N():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_GPIOR_PLL_SYS_RESET_N():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_GPIOR_PLL_SYS_SYNC_N():
	return WBGEN2_GEN_MASK(2, 1)
def DDS_GPIOR_PLL_SYS_LD():
	return WBGEN2_GEN_MASK(3, 1)
def DDS_GPIOR_PLL_SCLK():
	return WBGEN2_GEN_MASK(4, 1)
def DDS_GPIOR_PLL_SDIO():
	return WBGEN2_GEN_MASK(5, 1)
def DDS_GPIOR_PLL_SDIO_DIR():
	return WBGEN2_GEN_MASK(6, 1)
def DDS_GPIOR_PLL_VCXO_STATUS_N():
	return WBGEN2_GEN_MASK(7, 1)
def DDS_GPIOR_PLL_VCXO_CS_N():
	return WBGEN2_GEN_MASK(8, 1)
def DDS_GPIOR_PLL_VCXO_FUNCTION():
	return WBGEN2_GEN_MASK(9, 1)
def DDS_GPIOR_PLL_VCXO_SDO():
	return WBGEN2_GEN_MASK(10, 1)
def DDS_GPIOR_ADF_CE():
	return WBGEN2_GEN_MASK(11, 1)
def DDS_GPIOR_ADF_CLK():
	return WBGEN2_GEN_MASK(12, 1)
def DDS_GPIOR_ADF_LE():
	return WBGEN2_GEN_MASK(13, 1)
def DDS_GPIOR_ADF_DATA():
	return WBGEN2_GEN_MASK(14, 1)
def DDS_GPIOR_ADF_LD():
	return WBGEN2_GEN_MASK(15, 1)
def DDS_GPIOR_ADC_SDI():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_GPIOR_ADC_CNV():
	return WBGEN2_GEN_MASK(17, 1)
def DDS_GPIOR_ADC_SCK():
	return WBGEN2_GEN_MASK(18, 1)
def DDS_GPIOR_ADC_SDO():
	return WBGEN2_GEN_MASK(19, 1)
def DDS_GPIOR_FMC_PRESENT():
	return WBGEN2_GEN_MASK(20, 1)
def DDS_GPIOR_TEST_PLL_LD():
	return WBGEN2_GEN_MASK(21, 1)
def DDS_RSTR_PLL_RST():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_RSTR_SW_RST():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_RSTR_FREQ_RES():
	return WBGEN2_GEN_MASK(2, 1)
def DDS_I2CR_SCL_OUT():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_I2CR_SDA_OUT():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_I2CR_SCL_IN():
	return WBGEN2_GEN_MASK(2, 1)
def DDS_I2CR_SDA_IN():
	return WBGEN2_GEN_MASK(3, 1)
def DDS_PIR_KP_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_PIR_KI_MASK():
	return WBGEN2_GEN_MASK(16, 16)
def DDS_DLYR_DELAY_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_PHASER_PHASE_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_MACL_MACL_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_MACH_MACH_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_HIT_CNT_HIT_CNT_MASK():
	return WBGEN2_GEN_MASK(0, 24)
def DDS_MISS_CNT_MISS_CNT_MASK():
	return WBGEN2_GEN_MASK(0, 24)
def DDS_RX_CNT_RX_CNT_MASK():
	return WBGEN2_GEN_MASK(0, 24)
def DDS_TX_CNT_TX_CNT_MASK():
	return WBGEN2_GEN_MASK(0, 24)
def DDS_PLL_LD():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_GW_ID_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_DAC_AMPL_MASK():
	return WBGEN2_GEN_MASK(0, 14)
def DDS_DAC_EN():
	return WBGEN2_GEN_MASK(14, 1)
def DDS_DAC_TYPE_MASK():
	return WBGEN2_GEN_MASK(15, 2)
def DDS_TEST_COMM_REG_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_TEST_COMM_LED_R():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_TEST_COMM_LED_G():
	return WBGEN2_GEN_MASK(17, 1)
def DDS_FPGACTRL_MAINPLL():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_FPGAPLL_CLK2_CTRL_RST():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_FPGAPLL_CLK2_STAT_LOCK():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_CLK0_FREQ_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_CLK1_FREQ_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_CLK2_FREQ_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_PDTEST_PERIOD_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_OSCDAC_DATA_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_OSCDAC_LOAD():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_ADCINTERFACE_SOURCE():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_ADCINTERFACE_TRIGGER():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_DELAY_VALUE_MASK():
	return WBGEN2_GEN_MASK(0, 10)
def DDS_DELAY_ENABLE():
	return WBGEN2_GEN_MASK(10, 1)
def DDS_DELAY_LOAD():
	return WBGEN2_GEN_MASK(11, 1)
def DDS_DELAY_MAXVAL_MASK():
	return WBGEN2_GEN_MASK(12, 16)
def DDS_DELPHASE_STABLE():
	return WBGEN2_GEN_MASK(0, 1)
def DDS_DELPHASE_VALUE():
	return WBGEN2_GEN_MASK(1, 1)
def DDS_TRIGGER_FREQ_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_PD_FIFO_R0_DATA_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_PD_FIFO_CSR_FULL():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_PD_FIFO_CSR_EMPTY():
	return WBGEN2_GEN_MASK(17, 1)
def DDS_TUNE_FIFO_R0_DATA_MASK():
	return WBGEN2_GEN_MASK(0, 32)
def DDS_TUNE_FIFO_CSR_FULL():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_TUNE_FIFO_CSR_EMPTY():
	return WBGEN2_GEN_MASK(17, 1)
def DDS_PI_R0_DATA_MASK():
	return WBGEN2_GEN_MASK(0, 16)
def DDS_PI_CSR_FULL():
	return WBGEN2_GEN_MASK(16, 1)
def DDS_PI_CSR_EMPTY():
	return WBGEN2_GEN_MASK(17, 1)
def DDS_CR_CLK_ID_W(value):
	return WBGEN2_GEN_WRITE(value, 16, 16)
def DDS_PIR_KP_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_PIR_KI_W(value):
	return WBGEN2_GEN_WRITE(value, 16, 16)
def DDS_DLYR_DELAY_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_PHASER_PHASE_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_MACL_MACL_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_MACH_MACH_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_HIT_CNT_HIT_CNT_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 24)
def DDS_MISS_CNT_MISS_CNT_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 24)
def DDS_RX_CNT_RX_CNT_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 24)
def DDS_TX_CNT_TX_CNT_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 24)
def DDS_GW_ID_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_DAC_AMPL_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 14)
def DDS_DAC_TYPE_W(value):
	return WBGEN2_GEN_WRITE(value, 15, 2)
def DDS_TEST_COMM_REG_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_CLK0_FREQ_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_CLK1_FREQ_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_CLK2_FREQ_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_PDTEST_PERIOD_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_OSCDAC_DATA_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_DELAY_VALUE_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 10)
def DDS_DELAY_MAXVAL_W(value):
	return WBGEN2_GEN_WRITE(value, 12, 16)
def DDS_TRIGGER_FREQ_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_PD_FIFO_R0_DATA_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_TUNE_FIFO_R0_DATA_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 32)
def DDS_PI_R0_DATA_W(value):
	return WBGEN2_GEN_WRITE(value, 0, 16)
def DDS_CR_CLK_ID_R(reg):
	return WBGEN2_GEN_READ(reg, 16, 16)
def DDS_PIR_KP_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_PIR_KI_R(reg):
	return WBGEN2_GEN_READ(reg, 16, 16)
def DDS_DLYR_DELAY_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_PHASER_PHASE_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_MACL_MACL_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_MACH_MACH_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_HIT_CNT_HIT_CNT_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 24)
def DDS_MISS_CNT_MISS_CNT_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 24)
def DDS_RX_CNT_RX_CNT_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 24)
def DDS_TX_CNT_TX_CNT_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 24)
def DDS_GW_ID_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_DAC_AMPL_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 14)
def DDS_DAC_TYPE_R(reg):
	return WBGEN2_GEN_READ(reg, 15, 2)
def DDS_TEST_COMM_REG_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_CLK0_FREQ_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_CLK1_FREQ_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_CLK2_FREQ_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_PDTEST_PERIOD_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_OSCDAC_DATA_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_DELAY_VALUE_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 10)
def DDS_DELAY_MAXVAL_R(reg):
	return WBGEN2_GEN_READ(reg, 12, 16)
def DDS_TRIGGER_FREQ_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_PD_FIFO_R0_DATA_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
def DDS_TUNE_FIFO_R0_DATA_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 32)
def DDS_PI_R0_DATA_R(reg):
	return WBGEN2_GEN_READ(reg, 0, 16)
