FMC DEL 1ns 4cha - stand-alone application
Project description
The FMC Delay 1ns-4cha is an FPGA Mezzanine Card (FMC – VITA 57 standard), whose main purpose is to produce pulses delayed by a user-programmed value with respect to the input trigger pulse. The card can also work as a Time to Digital converter (TDC) or as a programmable pulse generator triggering at a given TAI time. It is implemented using a dedicated time-to-digital converter ASIC, TDC-GPX, from the European company Acam.
The FMC Delay card must be used as part of a WR node (FMC/SPEC or FMC/SVEC) and has to go through a initialization process. For the FMC Delay, this process includes starting some built-in on-chip bus and IO controllers, programming the PLL contained on the mezzanine and calibrating the output stages. This calibration is performed in order to ensure that the delay introduced is consistent with the programmed settings minimizing jitter (performed using ACAM's TDC-GPX chip). In addition to that, as the calibration is temperature-dependent the FMC needs to be periodically recalibrated. When the node is plugged on a PC, the driver (through PCI/Genum) is entrusted with this task and therefore, a node incorporating this mezzanine could not be operated as a stand-alone one.
The software and gateware here developed allows stand-alone operation of the FMC Delay + SPEC. The code runs on a embedded LM32 processor that initialize / periodically recalibrate the mezzanine and also provide two mechanisms (local, via RS232 and remote, using CALoE) that permit users to work with a FMC Delay on-SPEC node as when plugged on a PC. Because we miss the support of the O.S. we provide software to properly substitute the fmc and spec driver functions while the compatibility with the FMC Delay driver is assured so functionality and programming interfaces are preserver as much as possible.
The gateware architecture is illustrated in this figure. The GN4124 core
has been replaced for a new softprocesor core that includes RS232
support for conguration/programming purposes and a UART selector that
allows to choose between its own UART o the one on the WRPC.
In the case of the software, because we lack of OS, the functions and
functionalities provided by the spec and fmc drivers, ZIO as well as the
libraries from the Linux headers (that are still needed) had been
replaced for new ones keeping the same interface. As the design is
trying to be FMC Delay driver-compatible, both, interface and function
implementations have been re-utilized.
The target is a fully operational stand-alone FMC Delay based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption.
Main Features
*T.B.D.
Project information
Contacts
Commercial producers
General question about project
- Javier Diaz, University of Granada, emailto:jda@ugr.es
Status
Date | Event |
16-05-2014 | Start of project |
29 May 2014