/*
  Register definitions for slave core: Fine Delay Wishbone slave

  * File           : fd_core.h
  * Author         : auto-generated by wbgen2 from fd_wishbone_slave.wb
  * Created        : Mon Oct 31 17:01:03 2011
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_FD_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_FD_WISHBONE_SLAVE_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Reset Register */

/* definitions for register: ID Register */

/* definitions for register: Global Control Register */

/* definitions for field: Bypass delay block in reg: Global Control Register */
#define FD_GCR_BYPASS                         WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Enable trigger input in reg: Global Control Register */
#define FD_GCR_INPUT_EN                       WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Internal Counter Sync in reg: Global Control Register */
#define FD_GCR_CSYNC_INT                      WBGEN2_GEN_MASK(2, 1)

/* definitions for field: White Rabbit Counter Sync in reg: Global Control Register */
#define FD_GCR_CSYNC_WR                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: White Rabbit Timecode Ready in reg: Global Control Register */
#define FD_GCR_WR_READY                       WBGEN2_GEN_MASK(4, 1)

/* definitions for field: White Rabbit Locking Enable in reg: Global Control Register */
#define FD_GCR_WR_LOCK_EN                     WBGEN2_GEN_MASK(5, 1)

/* definitions for field: White Rabbit Oscillator Locked in reg: Global Control Register */
#define FD_GCR_WR_LOCKED                      WBGEN2_GEN_MASK(6, 1)

/* definitions for register: TDC Address/Data Register */

/* definitions for field: DATA in reg: TDC Address/Data Register */
#define FD_TAR_DATA_MASK                      WBGEN2_GEN_MASK(0, 28)
#define FD_TAR_DATA_SHIFT                     0
#define FD_TAR_DATA_W(value)                  WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_TAR_DATA_R(reg)                    WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: ADDR in reg: TDC Address/Data Register */
#define FD_TAR_ADDR_MASK                      WBGEN2_GEN_MASK(28, 4)
#define FD_TAR_ADDR_SHIFT                     28
#define FD_TAR_ADDR_W(value)                  WBGEN2_GEN_WRITE(value, 28, 4)
#define FD_TAR_ADDR_R(reg)                    WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: TDC control/status reg */

/* definitions for field: Start TDC write in reg: TDC control/status reg */
#define FD_TDCSR_WRITE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Start TDC read in reg: TDC control/status reg */
#define FD_TDCSR_READ                         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Error flag in reg: TDC control/status reg */
#define FD_TDCSR_ERR                          WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Interrupt flag in reg: TDC control/status reg */
#define FD_TDCSR_INT                          WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Load flag in reg: TDC control/status reg */
#define FD_TDCSR_LOAD                         WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Empty flag in reg: TDC control/status reg */
#define FD_TDCSR_EMPTY                        WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Start enable in reg: TDC control/status reg */
#define FD_TDCSR_STOP_EN                      WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Start disable in reg: TDC control/status reg */
#define FD_TDCSR_START_DIS                    WBGEN2_GEN_MASK(7, 1)

/* definitions for field: Stop enable in reg: TDC control/status reg */
#define FD_TDCSR_START_EN                     WBGEN2_GEN_MASK(8, 1)

/* definitions for field: Stop disable in reg: TDC control/status reg */
#define FD_TDCSR_STOP_DIS                     WBGEN2_GEN_MASK(9, 1)

/* definitions for field: write 1: Pulse the Alutrigger line in reg: TDC control/status reg */
#define FD_TDCSR_ALUTRIG                      WBGEN2_GEN_MASK(10, 1)

/* definitions for register: Calibration register */

/* definitions for field: Triggers calibration pulses in reg: Calibration register */
#define FD_CALR_CAL_PULSE                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Enable pulse generation in reg: Calibration register */
#define FD_CALR_PSEL_MASK                     WBGEN2_GEN_MASK(1, 4)
#define FD_CALR_PSEL_SHIFT                    1
#define FD_CALR_PSEL_W(value)                 WBGEN2_GEN_WRITE(value, 1, 4)
#define FD_CALR_PSEL_R(reg)                   WBGEN2_GEN_READ(reg, 1, 4)

/* definitions for register: Acam to Delay line fractional part Scale Factor Register */

/* definitions for register: Acam Timestamp Merging Control Register */

/* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_C_THR_MASK                   WBGEN2_GEN_MASK(0, 4)
#define FD_ATMCR_C_THR_SHIFT                  0
#define FD_ATMCR_C_THR_W(value)               WBGEN2_GEN_WRITE(value, 0, 4)
#define FD_ATMCR_C_THR_R(reg)                 WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_F_THR_MASK                   WBGEN2_GEN_MASK(4, 23)
#define FD_ATMCR_F_THR_SHIFT                  4
#define FD_ATMCR_F_THR_W(value)               WBGEN2_GEN_WRITE(value, 4, 23)
#define FD_ATMCR_F_THR_R(reg)                 WBGEN2_GEN_READ(reg, 4, 23)

/* definitions for register: Acam Start Offset Register */

/* definitions for field: Start Offset in reg: Acam Start Offset Register */
#define FD_ASOR_OFFSET_MASK                   WBGEN2_GEN_MASK(0, 23)
#define FD_ASOR_OFFSET_SHIFT                  0
#define FD_ASOR_OFFSET_W(value)               WBGEN2_GEN_WRITE(value, 0, 23)
#define FD_ASOR_OFFSET_R(reg)                 WBGEN2_GEN_READ(reg, 0, 23)

/* definitions for register: Raw Input Events Counter Register  */

/* definitions for register: Tagged Input Events Counter Register  */

/* definitions for register: Input Event Processing Delay Register */

/* definitions for field: Reset stats in reg: Input Event Processing Delay Register */
#define FD_IEPD_RST_STAT                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Processing delay in reg: Input Event Processing Delay Register */
#define FD_IEPD_PDELAY_MASK                   WBGEN2_GEN_MASK(1, 8)
#define FD_IEPD_PDELAY_SHIFT                  1
#define FD_IEPD_PDELAY_W(value)               WBGEN2_GEN_WRITE(value, 1, 8)
#define FD_IEPD_PDELAY_R(reg)                 WBGEN2_GEN_READ(reg, 1, 8)

/* definitions for register: SPI Control Register */

/* definitions for field: Data in reg: SPI Control Register */
#define FD_SCR_DATA_MASK                      WBGEN2_GEN_MASK(0, 24)
#define FD_SCR_DATA_SHIFT                     0
#define FD_SCR_DATA_W(value)                  WBGEN2_GEN_WRITE(value, 0, 24)
#define FD_SCR_DATA_R(reg)                    WBGEN2_GEN_READ(reg, 0, 24)

/* definitions for field: Select DAC in reg: SPI Control Register */
#define FD_SCR_SEL_DAC                        WBGEN2_GEN_MASK(24, 1)

/* definitions for field: Select PLL in reg: SPI Control Register */
#define FD_SCR_SEL_PLL                        WBGEN2_GEN_MASK(25, 1)

/* definitions for field: Select GPIO in reg: SPI Control Register */
#define FD_SCR_SEL_GPIO                       WBGEN2_GEN_MASK(26, 1)

/* definitions for field: Ready flag in reg: SPI Control Register */
#define FD_SCR_READY                          WBGEN2_GEN_MASK(27, 1)

/* definitions for field: Clock Polarity in reg: SPI Control Register */
#define FD_SCR_CPOL                           WBGEN2_GEN_MASK(28, 1)

/* definitions for field: Transfer Start in reg: SPI Control Register */
#define FD_SCR_START                          WBGEN2_GEN_MASK(29, 1)

/* definitions for register: Reference Clock Rate Register */

/* definitions for register: Reference Clock Frequency Register */

/* definitions for register: Timestamp Buffer Control Register */

/* definitions for field: Buffer enable in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_ENABLE                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Buffer purge in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_PURGE                        WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Reset TS Sequence Number in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_RST_SEQ                      WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Buffer full in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_FULL                         WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Buffer empty in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_EMPTY                        WBGEN2_GEN_MASK(4, 1)

/* definitions for register: Timestamp Buffer Readout UTC Register */

/* definitions for register: Timestamp Buffer Readout Cycles Register */

/* definitions for register: Timestamp Buffer Readout Fine / Seq ID Register */

/* definitions for field: Fine Value [in phase units] in reg: Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_TSBR_FID_FINE_MASK                 WBGEN2_GEN_MASK(0, 12)
#define FD_TSBR_FID_FINE_SHIFT                0
#define FD_TSBR_FID_FINE_W(value)             WBGEN2_GEN_WRITE(value, 0, 12)
#define FD_TSBR_FID_FINE_R(reg)               WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Timestamp Sequence ID in reg: Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_TSBR_FID_SEQID_MASK                WBGEN2_GEN_MASK(16, 16)
#define FD_TSBR_FID_SEQID_SHIFT               16
#define FD_TSBR_FID_SEQID_W(value)            WBGEN2_GEN_WRITE(value, 16, 16)
#define FD_TSBR_FID_SEQID_R(reg)              WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: I2C bitbanged IO register */

/* definitions for field: SCL Line out in reg: I2C bitbanged IO register */
#define FD_I2CR_SCL_OUT                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: SDA Line out in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_OUT                       WBGEN2_GEN_MASK(1, 1)

/* definitions for field: SCL Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SCL_IN                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_IN                        WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Delay Control Register (channel 1) */

/* definitions for field: Enable channel in reg: Delay Control Register (channel 1) */
#define FD_DCR1_ENABLE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Delay mode select in reg: Delay Control Register (channel 1) */
#define FD_DCR1_MODE                          WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 1) */
#define FD_DCR1_PG_ARM                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 1) */
#define FD_DCR1_PG_TRIG                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 1) */
#define FD_DCR1_UPDATE                        WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 1) */
#define FD_DCR1_UPD_DONE                      WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 1) */
#define FD_DCR1_FORCE_DLY                     WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Output Polarity in reg: Delay Control Register (channel 1) */
#define FD_DCR1_POL                           WBGEN2_GEN_MASK(7, 1)

/* definitions for register: Fine Range Register (channel 1) */

/* definitions for register: Pulse start time / offset (UTC part, channel 1) */

/* definitions for register: Pulse start time / offset (8 ns cycles, channel 1) */

/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 1) */

/* definitions for register: Pulse end time / offset (UTC part, channel 1) */

/* definitions for register: Pulse end time / offset (8 ns cycles, channel 1) */

/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 1) */

/* definitions for register: Delay Control Register (channel 2) */

/* definitions for field: Enable channel in reg: Delay Control Register (channel 2) */
#define FD_DCR2_ENABLE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Delay mode select in reg: Delay Control Register (channel 2) */
#define FD_DCR2_MODE                          WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 2) */
#define FD_DCR2_PG_ARM                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 2) */
#define FD_DCR2_PG_TRIG                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 2) */
#define FD_DCR2_UPDATE                        WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 2) */
#define FD_DCR2_UPD_DONE                      WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 2) */
#define FD_DCR2_FORCE_DLY                     WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Output Polarity in reg: Delay Control Register (channel 2) */
#define FD_DCR2_POL                           WBGEN2_GEN_MASK(7, 1)

/* definitions for register: Fine Range Register (channel 2) */

/* definitions for register: Pulse start time / offset (UTC part, channel 2) */

/* definitions for register: Pulse start time / offset (8 ns cycles, channel 2) */

/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 2) */

/* definitions for register: Pulse end time / offset (UTC part, channel 2) */

/* definitions for register: Pulse end time / offset (8 ns cycles, channel 2) */

/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 2) */

/* definitions for register: Delay Control Register (channel 3) */

/* definitions for field: Enable channel in reg: Delay Control Register (channel 3) */
#define FD_DCR3_ENABLE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Delay mode select in reg: Delay Control Register (channel 3) */
#define FD_DCR3_MODE                          WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 3) */
#define FD_DCR3_PG_ARM                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 3) */
#define FD_DCR3_PG_TRIG                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 3) */
#define FD_DCR3_UPDATE                        WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 3) */
#define FD_DCR3_UPD_DONE                      WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 3) */
#define FD_DCR3_FORCE_DLY                     WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Output Polarity in reg: Delay Control Register (channel 3) */
#define FD_DCR3_POL                           WBGEN2_GEN_MASK(7, 1)

/* definitions for register: Fine Range Register (channel 3) */

/* definitions for register: Pulse start time / offset (UTC part, channel 3) */

/* definitions for register: Pulse start time / offset (8 ns cycles, channel 3) */

/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 3) */

/* definitions for register: Pulse end time / offset (UTC part, channel 3) */

/* definitions for register: Pulse end time / offset (8 ns cycles, channel 3) */

/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 3) */

/* definitions for register: Delay Control Register (channel 4) */

/* definitions for field: Enable channel in reg: Delay Control Register (channel 4) */
#define FD_DCR4_ENABLE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Delay mode select in reg: Delay Control Register (channel 4) */
#define FD_DCR4_MODE                          WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 4) */
#define FD_DCR4_PG_ARM                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 4) */
#define FD_DCR4_PG_TRIG                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 4) */
#define FD_DCR4_UPDATE                        WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 4) */
#define FD_DCR4_UPD_DONE                      WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 4) */
#define FD_DCR4_FORCE_DLY                     WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Output Polarity in reg: Delay Control Register (channel 4) */
#define FD_DCR4_POL                           WBGEN2_GEN_MASK(7, 1)

/* definitions for register: Fine Range Register (channel 4) */

/* definitions for register: Pulse start time / offset (UTC part, channel 4) */

/* definitions for register: Pulse start time / offset (8 ns cycles, channel 4) */

/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 4) */

/* definitions for register: Pulse end time / offset (UTC part, channel 4) */

/* definitions for register: Pulse end time / offset (8 ns cycles, channel 4) */

/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 4) */

/* definitions for register: Interrupt disable register */

/* definitions for field: TS Buffer not empty in reg: Interrupt disable register */
#define FD_EIC_IDR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: TS Buffer not empty in reg: Interrupt enable register */
#define FD_EIC_IER_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: TS Buffer not empty in reg: Interrupt mask register */
#define FD_EIC_IMR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: TS Buffer not empty in reg: Interrupt status register */
#define FD_EIC_ISR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)

/* definitions for register: FIFO 'RAW FIFO' data output register 0 */

/* definitions for field: RawFrac in reg: FIFO 'RAW FIFO' data output register 0 */
#define FD_RAWFIFO_R0_FRAC_MASK               WBGEN2_GEN_MASK(0, 28)
#define FD_RAWFIFO_R0_FRAC_SHIFT              0
#define FD_RAWFIFO_R0_FRAC_W(value)           WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_RAWFIFO_R0_FRAC_R(reg)             WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for register: FIFO 'RAW FIFO' data output register 1 */

/* definitions for field: RawCoarse in reg: FIFO 'RAW FIFO' data output register 1 */
#define FD_RAWFIFO_R1_COARSE_MASK             WBGEN2_GEN_MASK(0, 28)
#define FD_RAWFIFO_R1_COARSE_SHIFT            0
#define FD_RAWFIFO_R1_COARSE_W(value)         WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_RAWFIFO_R1_COARSE_R(reg)           WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for register: FIFO 'RAW FIFO' control/status register */

/* definitions for field: FIFO empty flag in reg: FIFO 'RAW FIFO' control/status register */
#define FD_RAWFIFO_CSR_EMPTY                  WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG Reset Register */
#define FD_REG_RSTR 0x00000000
/* [0x4]: REG ID Register */
#define FD_REG_IDR 0x00000004
/* [0x8]: REG Global Control Register */
#define FD_REG_GCR 0x00000008
/* [0xc]: REG TDC Address/Data Register */
#define FD_REG_TAR 0x0000000c
/* [0x10]: REG TDC control/status reg */
#define FD_REG_TDCSR 0x00000010
/* [0x14]: REG Calibration register */
#define FD_REG_CALR 0x00000014
/* [0x18]: REG Acam to Delay line fractional part Scale Factor Register */
#define FD_REG_ADSFR 0x00000018
/* [0x1c]: REG Acam Timestamp Merging Control Register */
#define FD_REG_ATMCR 0x0000001c
/* [0x20]: REG Acam Start Offset Register */
#define FD_REG_ASOR 0x00000020
/* [0x24]: REG Raw Input Events Counter Register  */
#define FD_REG_IECRAW 0x00000024
/* [0x28]: REG Tagged Input Events Counter Register  */
#define FD_REG_IECTAG 0x00000028
/* [0x2c]: REG Input Event Processing Delay Register */
#define FD_REG_IEPD 0x0000002c
/* [0x30]: REG SPI Control Register */
#define FD_REG_SCR 0x00000030
/* [0x34]: REG Reference Clock Rate Register */
#define FD_REG_RCRR 0x00000034
/* [0x38]: REG Reference Clock Frequency Register */
#define FD_REG_RCFR 0x00000038
/* [0x3c]: REG Timestamp Buffer Control Register */
#define FD_REG_TSBCR 0x0000003c
/* [0x40]: REG Timestamp Buffer Readout UTC Register */
#define FD_REG_TSBR_U 0x00000040
/* [0x44]: REG Timestamp Buffer Readout Cycles Register */
#define FD_REG_TSBR_C 0x00000044
/* [0x48]: REG Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_REG_TSBR_FID 0x00000048
/* [0x4c]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x0000004c
/* [0x60]: REG Delay Control Register (channel 1) */
#define FD_REG_DCR1 0x00000060
/* [0x64]: REG Fine Range Register (channel 1) */
#define FD_REG_FRR1 0x00000064
/* [0x68]: REG Pulse start time / offset (UTC part, channel 1) */
#define FD_REG_U_START1 0x00000068
/* [0x6c]: REG Pulse start time / offset (8 ns cycles, channel 1) */
#define FD_REG_C_START1 0x0000006c
/* [0x70]: REG Pulse start time / offset (sub-cycle fine part, channel 1) */
#define FD_REG_F_START1 0x00000070
/* [0x74]: REG Pulse end time / offset (UTC part, channel 1) */
#define FD_REG_U_END1 0x00000074
/* [0x78]: REG Pulse end time / offset (8 ns cycles, channel 1) */
#define FD_REG_C_END1 0x00000078
/* [0x7c]: REG Pulse end time / offset (sub-cycle fine part, channel 1) */
#define FD_REG_F_END1 0x0000007c
/* [0x80]: REG Delay Control Register (channel 2) */
#define FD_REG_DCR2 0x00000080
/* [0x84]: REG Fine Range Register (channel 2) */
#define FD_REG_FRR2 0x00000084
/* [0x88]: REG Pulse start time / offset (UTC part, channel 2) */
#define FD_REG_U_START2 0x00000088
/* [0x8c]: REG Pulse start time / offset (8 ns cycles, channel 2) */
#define FD_REG_C_START2 0x0000008c
/* [0x90]: REG Pulse start time / offset (sub-cycle fine part, channel 2) */
#define FD_REG_F_START2 0x00000090
/* [0x94]: REG Pulse end time / offset (UTC part, channel 2) */
#define FD_REG_U_END2 0x00000094
/* [0x98]: REG Pulse end time / offset (8 ns cycles, channel 2) */
#define FD_REG_C_END2 0x00000098
/* [0x9c]: REG Pulse end time / offset (sub-cycle fine part, channel 2) */
#define FD_REG_F_END2 0x0000009c
/* [0xa0]: REG Delay Control Register (channel 3) */
#define FD_REG_DCR3 0x000000a0
/* [0xa4]: REG Fine Range Register (channel 3) */
#define FD_REG_FRR3 0x000000a4
/* [0xa8]: REG Pulse start time / offset (UTC part, channel 3) */
#define FD_REG_U_START3 0x000000a8
/* [0xac]: REG Pulse start time / offset (8 ns cycles, channel 3) */
#define FD_REG_C_START3 0x000000ac
/* [0xb0]: REG Pulse start time / offset (sub-cycle fine part, channel 3) */
#define FD_REG_F_START3 0x000000b0
/* [0xb4]: REG Pulse end time / offset (UTC part, channel 3) */
#define FD_REG_U_END3 0x000000b4
/* [0xb8]: REG Pulse end time / offset (8 ns cycles, channel 3) */
#define FD_REG_C_END3 0x000000b8
/* [0xbc]: REG Pulse end time / offset (sub-cycle fine part, channel 3) */
#define FD_REG_F_END3 0x000000bc
/* [0xc0]: REG Delay Control Register (channel 4) */
#define FD_REG_DCR4 0x000000c0
/* [0xc4]: REG Fine Range Register (channel 4) */
#define FD_REG_FRR4 0x000000c4
/* [0xc8]: REG Pulse start time / offset (UTC part, channel 4) */
#define FD_REG_U_START4 0x000000c8
/* [0xcc]: REG Pulse start time / offset (8 ns cycles, channel 4) */
#define FD_REG_C_START4 0x000000cc
/* [0xd0]: REG Pulse start time / offset (sub-cycle fine part, channel 4) */
#define FD_REG_F_START4 0x000000d0
/* [0xd4]: REG Pulse end time / offset (UTC part, channel 4) */
#define FD_REG_U_END4 0x000000d4
/* [0xd8]: REG Pulse end time / offset (8 ns cycles, channel 4) */
#define FD_REG_C_END4 0x000000d8
/* [0xdc]: REG Pulse end time / offset (sub-cycle fine part, channel 4) */
#define FD_REG_F_END4 0x000000dc
/* [0xe0]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x000000e0
/* [0xe4]: REG Interrupt enable register */
#define FD_REG_EIC_IER 0x000000e4
/* [0xe8]: REG Interrupt mask register */
#define FD_REG_EIC_IMR 0x000000e8
/* [0xec]: REG Interrupt status register */
#define FD_REG_EIC_ISR 0x000000ec
/* [0xf0]: REG FIFO 'RAW FIFO' data output register 0 */
#define FD_REG_RAWFIFO_R0 0x000000f0
/* [0xf4]: REG FIFO 'RAW FIFO' data output register 1 */
#define FD_REG_RAWFIFO_R1 0x000000f4
/* [0xf8]: REG FIFO 'RAW FIFO' control/status register */
#define FD_REG_RAWFIFO_CSR 0x000000f8
#endif
