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-- Title          : Wishbone slave core for Fine Delay Wishbone slave
---------------------------------------------------------------------------------------
-- File           : fd_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created        : Thu Oct 27 17:38:05 2011
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

package fd_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_fd_in_registers is record
    gcr_wr_ready_i                           : std_logic;
    gcr_wr_locked_i                          : std_logic;
    tar_data_i                               : std_logic_vector(27 downto 0);
    tdcsr_err_i                              : std_logic;
    tdcsr_int_i                              : std_logic;
    tdcsr_load_i                             : std_logic;
    tdcsr_empty_i                            : std_logic;
    iecraw_i                                 : std_logic_vector(31 downto 0);
    iectag_i                                 : std_logic_vector(31 downto 0);
    iepd_pdelay_i                            : std_logic_vector(7 downto 0);
    scr_data_i                               : std_logic_vector(23 downto 0);
    scr_ready_i                              : std_logic;
    rcrr_i                                   : std_logic_vector(31 downto 0);
    rcfr_i                                   : std_logic_vector(31 downto 0);
    tsbcr_full_i                             : std_logic;
    tsbcr_empty_i                            : std_logic;
    tsbr_u_i                                 : std_logic_vector(31 downto 0);
    tsbr_c_i                                 : std_logic_vector(27 downto 0);
    tsbr_fid_fine_i                          : std_logic_vector(11 downto 0);
    tsbr_fid_seqid_i                         : std_logic_vector(15 downto 0);
    rawfifo_wr_req_i                         : std_logic;
    rawfifo_frac_i                           : std_logic_vector(27 downto 0);
    rawfifo_coarse_i                         : std_logic_vector(27 downto 0);
    dcr1_pg_arm_i                            : std_logic;
    dcr1_pg_trig_i                           : std_logic;
    dcr1_upd_done_i                          : std_logic;
    dcr2_pg_arm_i                            : std_logic;
    dcr2_pg_trig_i                           : std_logic;
    dcr2_upd_done_i                          : std_logic;
    dcr3_pg_arm_i                            : std_logic;
    dcr3_pg_trig_i                           : std_logic;
    dcr3_upd_done_i                          : std_logic;
    dcr4_pg_arm_i                            : std_logic;
    dcr4_pg_trig_i                           : std_logic;
    dcr4_upd_done_i                          : std_logic;
    end record;
  
  constant c_fd_in_registers_init_value: t_fd_in_registers := (
    gcr_wr_ready_i => '0',
    gcr_wr_locked_i => '0',
    tar_data_i => (others => '0'),
    tdcsr_err_i => '0',
    tdcsr_int_i => '0',
    tdcsr_load_i => '0',
    tdcsr_empty_i => '0',
    iecraw_i => (others => '0'),
    iectag_i => (others => '0'),
    iepd_pdelay_i => (others => '0'),
    scr_data_i => (others => '0'),
    scr_ready_i => '0',
    rcrr_i => (others => '0'),
    rcfr_i => (others => '0'),
    tsbcr_full_i => '0',
    tsbcr_empty_i => '0',
    tsbr_u_i => (others => '0'),
    tsbr_c_i => (others => '0'),
    tsbr_fid_fine_i => (others => '0'),
    tsbr_fid_seqid_i => (others => '0'),
    rawfifo_wr_req_i => '0',
    rawfifo_frac_i => (others => '0'),
    rawfifo_coarse_i => (others => '0'),
    dcr1_pg_arm_i => '0',
    dcr1_pg_trig_i => '0',
    dcr1_upd_done_i => '0',
    dcr2_pg_arm_i => '0',
    dcr2_pg_trig_i => '0',
    dcr2_upd_done_i => '0',
    dcr3_pg_arm_i => '0',
    dcr3_pg_trig_i => '0',
    dcr3_upd_done_i => '0',
    dcr4_pg_arm_i => '0',
    dcr4_pg_trig_i => '0',
    dcr4_upd_done_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_fd_out_registers is record
      rstr_o                                   : std_logic_vector(31 downto 0);
      rstr_wr_o                                : std_logic;
      gcr_bypass_o                             : std_logic;
      gcr_input_en_o                           : std_logic;
      gcr_csync_int_o                          : std_logic;
      gcr_csync_wr_o                           : std_logic;
      gcr_wr_lock_en_o                         : std_logic;
      tar_data_o                               : std_logic_vector(27 downto 0);
      tar_data_load_o                          : std_logic;
      tar_addr_o                               : std_logic_vector(3 downto 0);
      tdcsr_write_o                            : std_logic;
      tdcsr_read_o                             : std_logic;
      tdcsr_stop_en_o                          : std_logic;
      tdcsr_start_dis_o                        : std_logic;
      tdcsr_start_en_o                         : std_logic;
      tdcsr_stop_dis_o                         : std_logic;
      tdcsr_alutrig_o                          : std_logic;
      calr_cal_pulse_o                         : std_logic;
      calr_psel_o                              : std_logic_vector(3 downto 0);
      adsfr_o                                  : std_logic_vector(17 downto 0);
      atmcr_c_thr_o                            : std_logic_vector(3 downto 0);
      atmcr_f_thr_o                            : std_logic_vector(22 downto 0);
      asor_offset_o                            : std_logic_vector(22 downto 0);
      iepd_rst_stat_o                          : std_logic;
      scr_data_o                               : std_logic_vector(23 downto 0);
      scr_data_load_o                          : std_logic;
      scr_sel_dac_o                            : std_logic;
      scr_sel_pll_o                            : std_logic;
      scr_sel_gpio_o                           : std_logic;
      scr_cpol_o                               : std_logic;
      scr_start_o                              : std_logic;
      tsbcr_enable_o                           : std_logic;
      tsbcr_purge_o                            : std_logic;
      tsbcr_rst_seq_o                          : std_logic;
      rawfifo_wr_full_o                        : std_logic;
      dcr1_enable_o                            : std_logic;
      dcr1_mode_o                              : std_logic;
      dcr1_pg_arm_o                            : std_logic;
      dcr1_pg_arm_load_o                       : std_logic;
      dcr1_update_o                            : std_logic;
      dcr1_force_dly_o                         : std_logic;
      dcr1_pol_o                               : std_logic;
      frr1_o                                   : std_logic_vector(9 downto 0);
      u_start1_o                               : std_logic_vector(31 downto 0);
      c_start1_o                               : std_logic_vector(27 downto 0);
      f_start1_o                               : std_logic_vector(11 downto 0);
      u_end1_o                                 : std_logic_vector(31 downto 0);
      c_end1_o                                 : std_logic_vector(27 downto 0);
      f_end1_o                                 : std_logic_vector(11 downto 0);
      dcr2_enable_o                            : std_logic;
      dcr2_mode_o                              : std_logic;
      dcr2_pg_arm_o                            : std_logic;
      dcr2_pg_arm_load_o                       : std_logic;
      dcr2_update_o                            : std_logic;
      dcr2_force_dly_o                         : std_logic;
      dcr2_pol_o                               : std_logic;
      frr2_o                                   : std_logic_vector(9 downto 0);
      u_start2_o                               : std_logic_vector(31 downto 0);
      c_start2_o                               : std_logic_vector(27 downto 0);
      f_start2_o                               : std_logic_vector(11 downto 0);
      u_end2_o                                 : std_logic_vector(31 downto 0);
      c_end2_o                                 : std_logic_vector(27 downto 0);
      f_end2_o                                 : std_logic_vector(11 downto 0);
      dcr3_enable_o                            : std_logic;
      dcr3_mode_o                              : std_logic;
      dcr3_pg_arm_o                            : std_logic;
      dcr3_pg_arm_load_o                       : std_logic;
      dcr3_update_o                            : std_logic;
      dcr3_force_dly_o                         : std_logic;
      dcr3_pol_o                               : std_logic;
      frr3_o                                   : std_logic_vector(9 downto 0);
      u_start3_o                               : std_logic_vector(31 downto 0);
      c_start3_o                               : std_logic_vector(27 downto 0);
      f_start3_o                               : std_logic_vector(11 downto 0);
      u_end3_o                                 : std_logic_vector(31 downto 0);
      c_end3_o                                 : std_logic_vector(27 downto 0);
      f_end3_o                                 : std_logic_vector(11 downto 0);
      dcr4_enable_o                            : std_logic;
      dcr4_mode_o                              : std_logic;
      dcr4_pg_arm_o                            : std_logic;
      dcr4_pg_arm_load_o                       : std_logic;
      dcr4_update_o                            : std_logic;
      dcr4_force_dly_o                         : std_logic;
      dcr4_pol_o                               : std_logic;
      frr4_o                                   : std_logic_vector(9 downto 0);
      u_start4_o                               : std_logic_vector(31 downto 0);
      c_start4_o                               : std_logic_vector(27 downto 0);
      f_start4_o                               : std_logic_vector(11 downto 0);
      u_end4_o                                 : std_logic_vector(31 downto 0);
      c_end4_o                                 : std_logic_vector(27 downto 0);
      f_end4_o                                 : std_logic_vector(11 downto 0);
      end record;
    
    constant c_fd_out_registers_init_value: t_fd_out_registers := (
      rstr_o => (others => '0'),
      rstr_wr_o => '0',
      gcr_bypass_o => '0',
      gcr_input_en_o => '0',
      gcr_csync_int_o => '0',
      gcr_csync_wr_o => '0',
      gcr_wr_lock_en_o => '0',
      tar_data_o => (others => '0'),
      tar_data_load_o => '0',
      tar_addr_o => (others => '0'),
      tdcsr_write_o => '0',
      tdcsr_read_o => '0',
      tdcsr_stop_en_o => '0',
      tdcsr_start_dis_o => '0',
      tdcsr_start_en_o => '0',
      tdcsr_stop_dis_o => '0',
      tdcsr_alutrig_o => '0',
      calr_cal_pulse_o => '0',
      calr_psel_o => (others => '0'),
      adsfr_o => (others => '0'),
      atmcr_c_thr_o => (others => '0'),
      atmcr_f_thr_o => (others => '0'),
      asor_offset_o => (others => '0'),
      iepd_rst_stat_o => '0',
      scr_data_o => (others => '0'),
      scr_data_load_o => '0',
      scr_sel_dac_o => '0',
      scr_sel_pll_o => '0',
      scr_sel_gpio_o => '0',
      scr_cpol_o => '0',
      scr_start_o => '0',
      tsbcr_enable_o => '0',
      tsbcr_purge_o => '0',
      tsbcr_rst_seq_o => '0',
      rawfifo_wr_full_o => '0',
      dcr1_enable_o => '0',
      dcr1_mode_o => '0',
      dcr1_pg_arm_o => '0',
      dcr1_pg_arm_load_o => '0',
      dcr1_update_o => '0',
      dcr1_force_dly_o => '0',
      dcr1_pol_o => '0',
      frr1_o => (others => '0'),
      u_start1_o => (others => '0'),
      c_start1_o => (others => '0'),
      f_start1_o => (others => '0'),
      u_end1_o => (others => '0'),
      c_end1_o => (others => '0'),
      f_end1_o => (others => '0'),
      dcr2_enable_o => '0',
      dcr2_mode_o => '0',
      dcr2_pg_arm_o => '0',
      dcr2_pg_arm_load_o => '0',
      dcr2_update_o => '0',
      dcr2_force_dly_o => '0',
      dcr2_pol_o => '0',
      frr2_o => (others => '0'),
      u_start2_o => (others => '0'),
      c_start2_o => (others => '0'),
      f_start2_o => (others => '0'),
      u_end2_o => (others => '0'),
      c_end2_o => (others => '0'),
      f_end2_o => (others => '0'),
      dcr3_enable_o => '0',
      dcr3_mode_o => '0',
      dcr3_pg_arm_o => '0',
      dcr3_pg_arm_load_o => '0',
      dcr3_update_o => '0',
      dcr3_force_dly_o => '0',
      dcr3_pol_o => '0',
      frr3_o => (others => '0'),
      u_start3_o => (others => '0'),
      c_start3_o => (others => '0'),
      f_start3_o => (others => '0'),
      u_end3_o => (others => '0'),
      c_end3_o => (others => '0'),
      f_end3_o => (others => '0'),
      dcr4_enable_o => '0',
      dcr4_mode_o => '0',
      dcr4_pg_arm_o => '0',
      dcr4_pg_arm_load_o => '0',
      dcr4_update_o => '0',
      dcr4_force_dly_o => '0',
      dcr4_pol_o => '0',
      frr4_o => (others => '0'),
      u_start4_o => (others => '0'),
      c_start4_o => (others => '0'),
      f_start4_o => (others => '0'),
      u_end4_o => (others => '0'),
      c_end4_o => (others => '0'),
      f_end4_o => (others => '0')
      );
    function "or" (left, right: t_fd_in_registers) return t_fd_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
end package;

package body fd_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function "or" (left, right: t_fd_in_registers) return t_fd_in_registers is
variable tmp: t_fd_in_registers;
begin
tmp.gcr_wr_ready_i := left.gcr_wr_ready_i or right.gcr_wr_ready_i;
tmp.gcr_wr_locked_i := left.gcr_wr_locked_i or right.gcr_wr_locked_i;
tmp.tar_data_i := left.tar_data_i or right.tar_data_i;
tmp.tdcsr_err_i := left.tdcsr_err_i or right.tdcsr_err_i;
tmp.tdcsr_int_i := left.tdcsr_int_i or right.tdcsr_int_i;
tmp.tdcsr_load_i := left.tdcsr_load_i or right.tdcsr_load_i;
tmp.tdcsr_empty_i := left.tdcsr_empty_i or right.tdcsr_empty_i;
tmp.iecraw_i := left.iecraw_i or right.iecraw_i;
tmp.iectag_i := left.iectag_i or right.iectag_i;
tmp.iepd_pdelay_i := left.iepd_pdelay_i or right.iepd_pdelay_i;
tmp.scr_data_i := left.scr_data_i or right.scr_data_i;
tmp.scr_ready_i := left.scr_ready_i or right.scr_ready_i;
tmp.rcrr_i := left.rcrr_i or right.rcrr_i;
tmp.rcfr_i := left.rcfr_i or right.rcfr_i;
tmp.tsbcr_full_i := left.tsbcr_full_i or right.tsbcr_full_i;
tmp.tsbcr_empty_i := left.tsbcr_empty_i or right.tsbcr_empty_i;
tmp.tsbr_u_i := left.tsbr_u_i or right.tsbr_u_i;
tmp.tsbr_c_i := left.tsbr_c_i or right.tsbr_c_i;
tmp.tsbr_fid_fine_i := left.tsbr_fid_fine_i or right.tsbr_fid_fine_i;
tmp.tsbr_fid_seqid_i := left.tsbr_fid_seqid_i or right.tsbr_fid_seqid_i;
tmp.rawfifo_wr_req_i := left.rawfifo_wr_req_i or right.rawfifo_wr_req_i;
tmp.rawfifo_frac_i := left.rawfifo_frac_i or right.rawfifo_frac_i;
tmp.rawfifo_coarse_i := left.rawfifo_coarse_i or right.rawfifo_coarse_i;
tmp.dcr1_pg_arm_i := left.dcr1_pg_arm_i or right.dcr1_pg_arm_i;
tmp.dcr1_pg_trig_i := left.dcr1_pg_trig_i or right.dcr1_pg_trig_i;
tmp.dcr1_upd_done_i := left.dcr1_upd_done_i or right.dcr1_upd_done_i;
tmp.dcr2_pg_arm_i := left.dcr2_pg_arm_i or right.dcr2_pg_arm_i;
tmp.dcr2_pg_trig_i := left.dcr2_pg_trig_i or right.dcr2_pg_trig_i;
tmp.dcr2_upd_done_i := left.dcr2_upd_done_i or right.dcr2_upd_done_i;
tmp.dcr3_pg_arm_i := left.dcr3_pg_arm_i or right.dcr3_pg_arm_i;
tmp.dcr3_pg_trig_i := left.dcr3_pg_trig_i or right.dcr3_pg_trig_i;
tmp.dcr3_upd_done_i := left.dcr3_upd_done_i or right.dcr3_upd_done_i;
tmp.dcr4_pg_arm_i := left.dcr4_pg_arm_i or right.dcr4_pg_arm_i;
tmp.dcr4_pg_trig_i := left.dcr4_pg_trig_i or right.dcr4_pg_trig_i;
tmp.dcr4_upd_done_i := left.dcr4_upd_done_i or right.dcr4_upd_done_i;
return tmp;
end function;
end package body;
