---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for Fine Delay Wishbone slave
---------------------------------------------------------------------------------------
-- File           : fd_wishbone_slave.vhd
-- Author         : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created        : Thu Oct 27 17:38:05 2011
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

use work.fd_wbgen2_pkg.all;


entity fd_wishbone_slave is
  port (
    rst_n_i                                  : in     std_logic;
    wb_clk_i                                 : in     std_logic;
    wb_addr_i                                : in     std_logic_vector(5 downto 0);
    wb_data_i                                : in     std_logic_vector(31 downto 0);
    wb_data_o                                : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_irq_o                                 : out    std_logic;
    clk_ref_i                                : in     std_logic;
    irq_ts_buf_notempty_i                    : in     std_logic;
    advance_rbuf_o                           : out    std_logic;
    regs_i                                   : in     t_fd_in_registers;
    regs_o                                   : out    t_fd_out_registers
  );
end fd_wishbone_slave;

architecture syn of fd_wishbone_slave is

signal fd_gcr_bypass_int                        : std_logic      ;
signal fd_gcr_bypass_sync0                      : std_logic      ;
signal fd_gcr_bypass_sync1                      : std_logic      ;
signal fd_gcr_input_en_int                      : std_logic      ;
signal fd_gcr_input_en_sync0                    : std_logic      ;
signal fd_gcr_input_en_sync1                    : std_logic      ;
signal fd_gcr_csync_int_int                     : std_logic      ;
signal fd_gcr_csync_int_int_delay               : std_logic      ;
signal fd_gcr_csync_int_sync0                   : std_logic      ;
signal fd_gcr_csync_int_sync1                   : std_logic      ;
signal fd_gcr_csync_int_sync2                   : std_logic      ;
signal fd_gcr_csync_wr_int                      : std_logic      ;
signal fd_gcr_csync_wr_int_delay                : std_logic      ;
signal fd_gcr_csync_wr_sync0                    : std_logic      ;
signal fd_gcr_csync_wr_sync1                    : std_logic      ;
signal fd_gcr_csync_wr_sync2                    : std_logic      ;
signal fd_gcr_wr_lock_en_int                    : std_logic      ;
signal fd_tar_data_int_read                     : std_logic_vector(27 downto 0);
signal fd_tar_data_int_write                    : std_logic_vector(27 downto 0);
signal fd_tar_data_lw                           : std_logic      ;
signal fd_tar_data_lw_delay                     : std_logic      ;
signal fd_tar_data_lw_read_in_progress          : std_logic      ;
signal fd_tar_data_lw_s0                        : std_logic      ;
signal fd_tar_data_lw_s1                        : std_logic      ;
signal fd_tar_data_lw_s2                        : std_logic      ;
signal fd_tar_data_rwsel                        : std_logic      ;
signal fd_tar_addr_int                          : std_logic_vector(3 downto 0);
signal fd_tar_addr_swb                          : std_logic      ;
signal fd_tar_addr_swb_delay                    : std_logic      ;
signal fd_tar_addr_swb_s0                       : std_logic      ;
signal fd_tar_addr_swb_s1                       : std_logic      ;
signal fd_tar_addr_swb_s2                       : std_logic      ;
signal fd_tdcsr_write_int                       : std_logic      ;
signal fd_tdcsr_write_int_delay                 : std_logic      ;
signal fd_tdcsr_write_sync0                     : std_logic      ;
signal fd_tdcsr_write_sync1                     : std_logic      ;
signal fd_tdcsr_write_sync2                     : std_logic      ;
signal fd_tdcsr_read_int                        : std_logic      ;
signal fd_tdcsr_read_int_delay                  : std_logic      ;
signal fd_tdcsr_read_sync0                      : std_logic      ;
signal fd_tdcsr_read_sync1                      : std_logic      ;
signal fd_tdcsr_read_sync2                      : std_logic      ;
signal fd_tdcsr_err_sync0                       : std_logic      ;
signal fd_tdcsr_err_sync1                       : std_logic      ;
signal fd_tdcsr_int_sync0                       : std_logic      ;
signal fd_tdcsr_int_sync1                       : std_logic      ;
signal fd_tdcsr_load_sync0                      : std_logic      ;
signal fd_tdcsr_load_sync1                      : std_logic      ;
signal fd_tdcsr_empty_sync0                     : std_logic      ;
signal fd_tdcsr_empty_sync1                     : std_logic      ;
signal fd_tdcsr_stop_en_int                     : std_logic      ;
signal fd_tdcsr_stop_en_int_delay               : std_logic      ;
signal fd_tdcsr_stop_en_sync0                   : std_logic      ;
signal fd_tdcsr_stop_en_sync1                   : std_logic      ;
signal fd_tdcsr_stop_en_sync2                   : std_logic      ;
signal fd_tdcsr_start_dis_int                   : std_logic      ;
signal fd_tdcsr_start_dis_int_delay             : std_logic      ;
signal fd_tdcsr_start_dis_sync0                 : std_logic      ;
signal fd_tdcsr_start_dis_sync1                 : std_logic      ;
signal fd_tdcsr_start_dis_sync2                 : std_logic      ;
signal fd_tdcsr_start_en_int                    : std_logic      ;
signal fd_tdcsr_start_en_int_delay              : std_logic      ;
signal fd_tdcsr_start_en_sync0                  : std_logic      ;
signal fd_tdcsr_start_en_sync1                  : std_logic      ;
signal fd_tdcsr_start_en_sync2                  : std_logic      ;
signal fd_tdcsr_stop_dis_int                    : std_logic      ;
signal fd_tdcsr_stop_dis_int_delay              : std_logic      ;
signal fd_tdcsr_stop_dis_sync0                  : std_logic      ;
signal fd_tdcsr_stop_dis_sync1                  : std_logic      ;
signal fd_tdcsr_stop_dis_sync2                  : std_logic      ;
signal fd_tdcsr_alutrig_int                     : std_logic      ;
signal fd_tdcsr_alutrig_int_delay               : std_logic      ;
signal fd_tdcsr_alutrig_sync0                   : std_logic      ;
signal fd_tdcsr_alutrig_sync1                   : std_logic      ;
signal fd_tdcsr_alutrig_sync2                   : std_logic      ;
signal fd_calr_cal_pulse_int                    : std_logic      ;
signal fd_calr_cal_pulse_int_delay              : std_logic      ;
signal fd_calr_cal_pulse_sync0                  : std_logic      ;
signal fd_calr_cal_pulse_sync1                  : std_logic      ;
signal fd_calr_cal_pulse_sync2                  : std_logic      ;
signal fd_calr_psel_int                         : std_logic_vector(3 downto 0);
signal fd_calr_psel_swb                         : std_logic      ;
signal fd_calr_psel_swb_delay                   : std_logic      ;
signal fd_calr_psel_swb_s0                      : std_logic      ;
signal fd_calr_psel_swb_s1                      : std_logic      ;
signal fd_calr_psel_swb_s2                      : std_logic      ;
signal fd_adsfr_int                             : std_logic_vector(17 downto 0);
signal fd_adsfr_swb                             : std_logic      ;
signal fd_adsfr_swb_delay                       : std_logic      ;
signal fd_adsfr_swb_s0                          : std_logic      ;
signal fd_adsfr_swb_s1                          : std_logic      ;
signal fd_adsfr_swb_s2                          : std_logic      ;
signal fd_atmcr_c_thr_int                       : std_logic_vector(3 downto 0);
signal fd_atmcr_c_thr_swb                       : std_logic      ;
signal fd_atmcr_c_thr_swb_delay                 : std_logic      ;
signal fd_atmcr_c_thr_swb_s0                    : std_logic      ;
signal fd_atmcr_c_thr_swb_s1                    : std_logic      ;
signal fd_atmcr_c_thr_swb_s2                    : std_logic      ;
signal fd_atmcr_f_thr_int                       : std_logic_vector(22 downto 0);
signal fd_atmcr_f_thr_swb                       : std_logic      ;
signal fd_atmcr_f_thr_swb_delay                 : std_logic      ;
signal fd_atmcr_f_thr_swb_s0                    : std_logic      ;
signal fd_atmcr_f_thr_swb_s1                    : std_logic      ;
signal fd_atmcr_f_thr_swb_s2                    : std_logic      ;
signal fd_asor_offset_int                       : std_logic_vector(22 downto 0);
signal fd_asor_offset_swb                       : std_logic      ;
signal fd_asor_offset_swb_delay                 : std_logic      ;
signal fd_asor_offset_swb_s0                    : std_logic      ;
signal fd_asor_offset_swb_s1                    : std_logic      ;
signal fd_asor_offset_swb_s2                    : std_logic      ;
signal fd_iecraw_int                            : std_logic_vector(31 downto 0);
signal fd_iecraw_lwb                            : std_logic      ;
signal fd_iecraw_lwb_delay                      : std_logic      ;
signal fd_iecraw_lwb_in_progress                : std_logic      ;
signal fd_iecraw_lwb_s0                         : std_logic      ;
signal fd_iecraw_lwb_s1                         : std_logic      ;
signal fd_iecraw_lwb_s2                         : std_logic      ;
signal fd_iectag_int                            : std_logic_vector(31 downto 0);
signal fd_iectag_lwb                            : std_logic      ;
signal fd_iectag_lwb_delay                      : std_logic      ;
signal fd_iectag_lwb_in_progress                : std_logic      ;
signal fd_iectag_lwb_s0                         : std_logic      ;
signal fd_iectag_lwb_s1                         : std_logic      ;
signal fd_iectag_lwb_s2                         : std_logic      ;
signal fd_iepd_rst_stat_int                     : std_logic      ;
signal fd_iepd_rst_stat_int_delay               : std_logic      ;
signal fd_iepd_rst_stat_sync0                   : std_logic      ;
signal fd_iepd_rst_stat_sync1                   : std_logic      ;
signal fd_iepd_rst_stat_sync2                   : std_logic      ;
signal fd_iepd_pdelay_int                       : std_logic_vector(7 downto 0);
signal fd_iepd_pdelay_lwb                       : std_logic      ;
signal fd_iepd_pdelay_lwb_delay                 : std_logic      ;
signal fd_iepd_pdelay_lwb_in_progress           : std_logic      ;
signal fd_iepd_pdelay_lwb_s0                    : std_logic      ;
signal fd_iepd_pdelay_lwb_s1                    : std_logic      ;
signal fd_iepd_pdelay_lwb_s2                    : std_logic      ;
signal fd_scr_sel_dac_int                       : std_logic      ;
signal fd_scr_sel_pll_int                       : std_logic      ;
signal fd_scr_sel_gpio_int                      : std_logic      ;
signal fd_scr_cpol_int                          : std_logic      ;
signal fd_scr_start_dly0                        : std_logic      ;
signal fd_scr_start_int                         : std_logic      ;
signal fd_rcrr_int                              : std_logic_vector(31 downto 0);
signal fd_rcrr_lwb                              : std_logic      ;
signal fd_rcrr_lwb_delay                        : std_logic      ;
signal fd_rcrr_lwb_in_progress                  : std_logic      ;
signal fd_rcrr_lwb_s0                           : std_logic      ;
signal fd_rcrr_lwb_s1                           : std_logic      ;
signal fd_rcrr_lwb_s2                           : std_logic      ;
signal fd_rcfr_int                              : std_logic_vector(31 downto 0);
signal fd_rcfr_lwb                              : std_logic      ;
signal fd_rcfr_lwb_delay                        : std_logic      ;
signal fd_rcfr_lwb_in_progress                  : std_logic      ;
signal fd_rcfr_lwb_s0                           : std_logic      ;
signal fd_rcfr_lwb_s1                           : std_logic      ;
signal fd_rcfr_lwb_s2                           : std_logic      ;
signal fd_tsbcr_enable_int                      : std_logic      ;
signal fd_tsbcr_purge_dly0                      : std_logic      ;
signal fd_tsbcr_purge_int                       : std_logic      ;
signal fd_tsbcr_rst_seq_int                     : std_logic      ;
signal fd_tsbcr_rst_seq_int_delay               : std_logic      ;
signal fd_tsbcr_rst_seq_sync0                   : std_logic      ;
signal fd_tsbcr_rst_seq_sync1                   : std_logic      ;
signal fd_tsbcr_rst_seq_sync2                   : std_logic      ;
signal fd_rawfifo_in_int                        : std_logic_vector(55 downto 0);
signal fd_rawfifo_out_int                       : std_logic_vector(55 downto 0);
signal fd_rawfifo_rdreq_int                     : std_logic      ;
signal fd_rawfifo_rdreq_int_d0                  : std_logic      ;
signal fd_dcr1_enable_int                       : std_logic      ;
signal fd_dcr1_enable_sync0                     : std_logic      ;
signal fd_dcr1_enable_sync1                     : std_logic      ;
signal fd_dcr1_mode_int                         : std_logic      ;
signal fd_dcr1_mode_sync0                       : std_logic      ;
signal fd_dcr1_mode_sync1                       : std_logic      ;
signal fd_dcr1_pg_arm_int_read                  : std_logic      ;
signal fd_dcr1_pg_arm_int_write                 : std_logic      ;
signal fd_dcr1_pg_arm_lw                        : std_logic      ;
signal fd_dcr1_pg_arm_lw_delay                  : std_logic      ;
signal fd_dcr1_pg_arm_lw_read_in_progress       : std_logic      ;
signal fd_dcr1_pg_arm_lw_s0                     : std_logic      ;
signal fd_dcr1_pg_arm_lw_s1                     : std_logic      ;
signal fd_dcr1_pg_arm_lw_s2                     : std_logic      ;
signal fd_dcr1_pg_arm_rwsel                     : std_logic      ;
signal fd_dcr1_pg_trig_sync0                    : std_logic      ;
signal fd_dcr1_pg_trig_sync1                    : std_logic      ;
signal fd_dcr1_update_int                       : std_logic      ;
signal fd_dcr1_update_int_delay                 : std_logic      ;
signal fd_dcr1_update_sync0                     : std_logic      ;
signal fd_dcr1_update_sync1                     : std_logic      ;
signal fd_dcr1_update_sync2                     : std_logic      ;
signal fd_dcr1_upd_done_sync0                   : std_logic      ;
signal fd_dcr1_upd_done_sync1                   : std_logic      ;
signal fd_dcr1_force_dly_int                    : std_logic      ;
signal fd_dcr1_force_dly_int_delay              : std_logic      ;
signal fd_dcr1_force_dly_sync0                  : std_logic      ;
signal fd_dcr1_force_dly_sync1                  : std_logic      ;
signal fd_dcr1_force_dly_sync2                  : std_logic      ;
signal fd_dcr1_pol_int                          : std_logic      ;
signal fd_dcr1_pol_sync0                        : std_logic      ;
signal fd_dcr1_pol_sync1                        : std_logic      ;
signal fd_frr1_int                              : std_logic_vector(9 downto 0);
signal fd_frr1_swb                              : std_logic      ;
signal fd_frr1_swb_delay                        : std_logic      ;
signal fd_frr1_swb_s0                           : std_logic      ;
signal fd_frr1_swb_s1                           : std_logic      ;
signal fd_frr1_swb_s2                           : std_logic      ;
signal fd_u_start1_int                          : std_logic_vector(31 downto 0);
signal fd_u_start1_swb                          : std_logic      ;
signal fd_u_start1_swb_delay                    : std_logic      ;
signal fd_u_start1_swb_s0                       : std_logic      ;
signal fd_u_start1_swb_s1                       : std_logic      ;
signal fd_u_start1_swb_s2                       : std_logic      ;
signal fd_c_start1_int                          : std_logic_vector(27 downto 0);
signal fd_c_start1_swb                          : std_logic      ;
signal fd_c_start1_swb_delay                    : std_logic      ;
signal fd_c_start1_swb_s0                       : std_logic      ;
signal fd_c_start1_swb_s1                       : std_logic      ;
signal fd_c_start1_swb_s2                       : std_logic      ;
signal fd_f_start1_int                          : std_logic_vector(11 downto 0);
signal fd_f_start1_swb                          : std_logic      ;
signal fd_f_start1_swb_delay                    : std_logic      ;
signal fd_f_start1_swb_s0                       : std_logic      ;
signal fd_f_start1_swb_s1                       : std_logic      ;
signal fd_f_start1_swb_s2                       : std_logic      ;
signal fd_u_end1_int                            : std_logic_vector(31 downto 0);
signal fd_u_end1_swb                            : std_logic      ;
signal fd_u_end1_swb_delay                      : std_logic      ;
signal fd_u_end1_swb_s0                         : std_logic      ;
signal fd_u_end1_swb_s1                         : std_logic      ;
signal fd_u_end1_swb_s2                         : std_logic      ;
signal fd_c_end1_int                            : std_logic_vector(27 downto 0);
signal fd_c_end1_swb                            : std_logic      ;
signal fd_c_end1_swb_delay                      : std_logic      ;
signal fd_c_end1_swb_s0                         : std_logic      ;
signal fd_c_end1_swb_s1                         : std_logic      ;
signal fd_c_end1_swb_s2                         : std_logic      ;
signal fd_f_end1_int                            : std_logic_vector(11 downto 0);
signal fd_f_end1_swb                            : std_logic      ;
signal fd_f_end1_swb_delay                      : std_logic      ;
signal fd_f_end1_swb_s0                         : std_logic      ;
signal fd_f_end1_swb_s1                         : std_logic      ;
signal fd_f_end1_swb_s2                         : std_logic      ;
signal fd_dcr2_enable_int                       : std_logic      ;
signal fd_dcr2_enable_sync0                     : std_logic      ;
signal fd_dcr2_enable_sync1                     : std_logic      ;
signal fd_dcr2_mode_int                         : std_logic      ;
signal fd_dcr2_mode_sync0                       : std_logic      ;
signal fd_dcr2_mode_sync1                       : std_logic      ;
signal fd_dcr2_pg_arm_int_read                  : std_logic      ;
signal fd_dcr2_pg_arm_int_write                 : std_logic      ;
signal fd_dcr2_pg_arm_lw                        : std_logic      ;
signal fd_dcr2_pg_arm_lw_delay                  : std_logic      ;
signal fd_dcr2_pg_arm_lw_read_in_progress       : std_logic      ;
signal fd_dcr2_pg_arm_lw_s0                     : std_logic      ;
signal fd_dcr2_pg_arm_lw_s1                     : std_logic      ;
signal fd_dcr2_pg_arm_lw_s2                     : std_logic      ;
signal fd_dcr2_pg_arm_rwsel                     : std_logic      ;
signal fd_dcr2_pg_trig_sync0                    : std_logic      ;
signal fd_dcr2_pg_trig_sync1                    : std_logic      ;
signal fd_dcr2_update_int                       : std_logic      ;
signal fd_dcr2_update_int_delay                 : std_logic      ;
signal fd_dcr2_update_sync0                     : std_logic      ;
signal fd_dcr2_update_sync1                     : std_logic      ;
signal fd_dcr2_update_sync2                     : std_logic      ;
signal fd_dcr2_upd_done_sync0                   : std_logic      ;
signal fd_dcr2_upd_done_sync1                   : std_logic      ;
signal fd_dcr2_force_dly_int                    : std_logic      ;
signal fd_dcr2_force_dly_int_delay              : std_logic      ;
signal fd_dcr2_force_dly_sync0                  : std_logic      ;
signal fd_dcr2_force_dly_sync1                  : std_logic      ;
signal fd_dcr2_force_dly_sync2                  : std_logic      ;
signal fd_dcr2_pol_int                          : std_logic      ;
signal fd_dcr2_pol_sync0                        : std_logic      ;
signal fd_dcr2_pol_sync1                        : std_logic      ;
signal fd_frr2_int                              : std_logic_vector(9 downto 0);
signal fd_frr2_swb                              : std_logic      ;
signal fd_frr2_swb_delay                        : std_logic      ;
signal fd_frr2_swb_s0                           : std_logic      ;
signal fd_frr2_swb_s1                           : std_logic      ;
signal fd_frr2_swb_s2                           : std_logic      ;
signal fd_u_start2_int                          : std_logic_vector(31 downto 0);
signal fd_u_start2_swb                          : std_logic      ;
signal fd_u_start2_swb_delay                    : std_logic      ;
signal fd_u_start2_swb_s0                       : std_logic      ;
signal fd_u_start2_swb_s1                       : std_logic      ;
signal fd_u_start2_swb_s2                       : std_logic      ;
signal fd_c_start2_int                          : std_logic_vector(27 downto 0);
signal fd_c_start2_swb                          : std_logic      ;
signal fd_c_start2_swb_delay                    : std_logic      ;
signal fd_c_start2_swb_s0                       : std_logic      ;
signal fd_c_start2_swb_s1                       : std_logic      ;
signal fd_c_start2_swb_s2                       : std_logic      ;
signal fd_f_start2_int                          : std_logic_vector(11 downto 0);
signal fd_f_start2_swb                          : std_logic      ;
signal fd_f_start2_swb_delay                    : std_logic      ;
signal fd_f_start2_swb_s0                       : std_logic      ;
signal fd_f_start2_swb_s1                       : std_logic      ;
signal fd_f_start2_swb_s2                       : std_logic      ;
signal fd_u_end2_int                            : std_logic_vector(31 downto 0);
signal fd_u_end2_swb                            : std_logic      ;
signal fd_u_end2_swb_delay                      : std_logic      ;
signal fd_u_end2_swb_s0                         : std_logic      ;
signal fd_u_end2_swb_s1                         : std_logic      ;
signal fd_u_end2_swb_s2                         : std_logic      ;
signal fd_c_end2_int                            : std_logic_vector(27 downto 0);
signal fd_c_end2_swb                            : std_logic      ;
signal fd_c_end2_swb_delay                      : std_logic      ;
signal fd_c_end2_swb_s0                         : std_logic      ;
signal fd_c_end2_swb_s1                         : std_logic      ;
signal fd_c_end2_swb_s2                         : std_logic      ;
signal fd_f_end2_int                            : std_logic_vector(11 downto 0);
signal fd_f_end2_swb                            : std_logic      ;
signal fd_f_end2_swb_delay                      : std_logic      ;
signal fd_f_end2_swb_s0                         : std_logic      ;
signal fd_f_end2_swb_s1                         : std_logic      ;
signal fd_f_end2_swb_s2                         : std_logic      ;
signal fd_dcr3_enable_int                       : std_logic      ;
signal fd_dcr3_enable_sync0                     : std_logic      ;
signal fd_dcr3_enable_sync1                     : std_logic      ;
signal fd_dcr3_mode_int                         : std_logic      ;
signal fd_dcr3_mode_sync0                       : std_logic      ;
signal fd_dcr3_mode_sync1                       : std_logic      ;
signal fd_dcr3_pg_arm_int_read                  : std_logic      ;
signal fd_dcr3_pg_arm_int_write                 : std_logic      ;
signal fd_dcr3_pg_arm_lw                        : std_logic      ;
signal fd_dcr3_pg_arm_lw_delay                  : std_logic      ;
signal fd_dcr3_pg_arm_lw_read_in_progress       : std_logic      ;
signal fd_dcr3_pg_arm_lw_s0                     : std_logic      ;
signal fd_dcr3_pg_arm_lw_s1                     : std_logic      ;
signal fd_dcr3_pg_arm_lw_s2                     : std_logic      ;
signal fd_dcr3_pg_arm_rwsel                     : std_logic      ;
signal fd_dcr3_pg_trig_sync0                    : std_logic      ;
signal fd_dcr3_pg_trig_sync1                    : std_logic      ;
signal fd_dcr3_update_int                       : std_logic      ;
signal fd_dcr3_update_int_delay                 : std_logic      ;
signal fd_dcr3_update_sync0                     : std_logic      ;
signal fd_dcr3_update_sync1                     : std_logic      ;
signal fd_dcr3_update_sync2                     : std_logic      ;
signal fd_dcr3_upd_done_sync0                   : std_logic      ;
signal fd_dcr3_upd_done_sync1                   : std_logic      ;
signal fd_dcr3_force_dly_int                    : std_logic      ;
signal fd_dcr3_force_dly_int_delay              : std_logic      ;
signal fd_dcr3_force_dly_sync0                  : std_logic      ;
signal fd_dcr3_force_dly_sync1                  : std_logic      ;
signal fd_dcr3_force_dly_sync2                  : std_logic      ;
signal fd_dcr3_pol_int                          : std_logic      ;
signal fd_dcr3_pol_sync0                        : std_logic      ;
signal fd_dcr3_pol_sync1                        : std_logic      ;
signal fd_frr3_int                              : std_logic_vector(9 downto 0);
signal fd_frr3_swb                              : std_logic      ;
signal fd_frr3_swb_delay                        : std_logic      ;
signal fd_frr3_swb_s0                           : std_logic      ;
signal fd_frr3_swb_s1                           : std_logic      ;
signal fd_frr3_swb_s2                           : std_logic      ;
signal fd_u_start3_int                          : std_logic_vector(31 downto 0);
signal fd_u_start3_swb                          : std_logic      ;
signal fd_u_start3_swb_delay                    : std_logic      ;
signal fd_u_start3_swb_s0                       : std_logic      ;
signal fd_u_start3_swb_s1                       : std_logic      ;
signal fd_u_start3_swb_s2                       : std_logic      ;
signal fd_c_start3_int                          : std_logic_vector(27 downto 0);
signal fd_c_start3_swb                          : std_logic      ;
signal fd_c_start3_swb_delay                    : std_logic      ;
signal fd_c_start3_swb_s0                       : std_logic      ;
signal fd_c_start3_swb_s1                       : std_logic      ;
signal fd_c_start3_swb_s2                       : std_logic      ;
signal fd_f_start3_int                          : std_logic_vector(11 downto 0);
signal fd_f_start3_swb                          : std_logic      ;
signal fd_f_start3_swb_delay                    : std_logic      ;
signal fd_f_start3_swb_s0                       : std_logic      ;
signal fd_f_start3_swb_s1                       : std_logic      ;
signal fd_f_start3_swb_s2                       : std_logic      ;
signal fd_u_end3_int                            : std_logic_vector(31 downto 0);
signal fd_u_end3_swb                            : std_logic      ;
signal fd_u_end3_swb_delay                      : std_logic      ;
signal fd_u_end3_swb_s0                         : std_logic      ;
signal fd_u_end3_swb_s1                         : std_logic      ;
signal fd_u_end3_swb_s2                         : std_logic      ;
signal fd_c_end3_int                            : std_logic_vector(27 downto 0);
signal fd_c_end3_swb                            : std_logic      ;
signal fd_c_end3_swb_delay                      : std_logic      ;
signal fd_c_end3_swb_s0                         : std_logic      ;
signal fd_c_end3_swb_s1                         : std_logic      ;
signal fd_c_end3_swb_s2                         : std_logic      ;
signal fd_f_end3_int                            : std_logic_vector(11 downto 0);
signal fd_f_end3_swb                            : std_logic      ;
signal fd_f_end3_swb_delay                      : std_logic      ;
signal fd_f_end3_swb_s0                         : std_logic      ;
signal fd_f_end3_swb_s1                         : std_logic      ;
signal fd_f_end3_swb_s2                         : std_logic      ;
signal fd_dcr4_enable_int                       : std_logic      ;
signal fd_dcr4_enable_sync0                     : std_logic      ;
signal fd_dcr4_enable_sync1                     : std_logic      ;
signal fd_dcr4_mode_int                         : std_logic      ;
signal fd_dcr4_mode_sync0                       : std_logic      ;
signal fd_dcr4_mode_sync1                       : std_logic      ;
signal fd_dcr4_pg_arm_int_read                  : std_logic      ;
signal fd_dcr4_pg_arm_int_write                 : std_logic      ;
signal fd_dcr4_pg_arm_lw                        : std_logic      ;
signal fd_dcr4_pg_arm_lw_delay                  : std_logic      ;
signal fd_dcr4_pg_arm_lw_read_in_progress       : std_logic      ;
signal fd_dcr4_pg_arm_lw_s0                     : std_logic      ;
signal fd_dcr4_pg_arm_lw_s1                     : std_logic      ;
signal fd_dcr4_pg_arm_lw_s2                     : std_logic      ;
signal fd_dcr4_pg_arm_rwsel                     : std_logic      ;
signal fd_dcr4_pg_trig_sync0                    : std_logic      ;
signal fd_dcr4_pg_trig_sync1                    : std_logic      ;
signal fd_dcr4_update_int                       : std_logic      ;
signal fd_dcr4_update_int_delay                 : std_logic      ;
signal fd_dcr4_update_sync0                     : std_logic      ;
signal fd_dcr4_update_sync1                     : std_logic      ;
signal fd_dcr4_update_sync2                     : std_logic      ;
signal fd_dcr4_upd_done_sync0                   : std_logic      ;
signal fd_dcr4_upd_done_sync1                   : std_logic      ;
signal fd_dcr4_force_dly_int                    : std_logic      ;
signal fd_dcr4_force_dly_int_delay              : std_logic      ;
signal fd_dcr4_force_dly_sync0                  : std_logic      ;
signal fd_dcr4_force_dly_sync1                  : std_logic      ;
signal fd_dcr4_force_dly_sync2                  : std_logic      ;
signal fd_dcr4_pol_int                          : std_logic      ;
signal fd_dcr4_pol_sync0                        : std_logic      ;
signal fd_dcr4_pol_sync1                        : std_logic      ;
signal fd_frr4_int                              : std_logic_vector(9 downto 0);
signal fd_frr4_swb                              : std_logic      ;
signal fd_frr4_swb_delay                        : std_logic      ;
signal fd_frr4_swb_s0                           : std_logic      ;
signal fd_frr4_swb_s1                           : std_logic      ;
signal fd_frr4_swb_s2                           : std_logic      ;
signal fd_u_start4_int                          : std_logic_vector(31 downto 0);
signal fd_u_start4_swb                          : std_logic      ;
signal fd_u_start4_swb_delay                    : std_logic      ;
signal fd_u_start4_swb_s0                       : std_logic      ;
signal fd_u_start4_swb_s1                       : std_logic      ;
signal fd_u_start4_swb_s2                       : std_logic      ;
signal fd_c_start4_int                          : std_logic_vector(27 downto 0);
signal fd_c_start4_swb                          : std_logic      ;
signal fd_c_start4_swb_delay                    : std_logic      ;
signal fd_c_start4_swb_s0                       : std_logic      ;
signal fd_c_start4_swb_s1                       : std_logic      ;
signal fd_c_start4_swb_s2                       : std_logic      ;
signal fd_f_start4_int                          : std_logic_vector(11 downto 0);
signal fd_f_start4_swb                          : std_logic      ;
signal fd_f_start4_swb_delay                    : std_logic      ;
signal fd_f_start4_swb_s0                       : std_logic      ;
signal fd_f_start4_swb_s1                       : std_logic      ;
signal fd_f_start4_swb_s2                       : std_logic      ;
signal fd_u_end4_int                            : std_logic_vector(31 downto 0);
signal fd_u_end4_swb                            : std_logic      ;
signal fd_u_end4_swb_delay                      : std_logic      ;
signal fd_u_end4_swb_s0                         : std_logic      ;
signal fd_u_end4_swb_s1                         : std_logic      ;
signal fd_u_end4_swb_s2                         : std_logic      ;
signal fd_c_end4_int                            : std_logic_vector(27 downto 0);
signal fd_c_end4_swb                            : std_logic      ;
signal fd_c_end4_swb_delay                      : std_logic      ;
signal fd_c_end4_swb_s0                         : std_logic      ;
signal fd_c_end4_swb_s1                         : std_logic      ;
signal fd_c_end4_swb_s2                         : std_logic      ;
signal fd_f_end4_int                            : std_logic_vector(11 downto 0);
signal fd_f_end4_swb                            : std_logic      ;
signal fd_f_end4_swb_delay                      : std_logic      ;
signal fd_f_end4_swb_s0                         : std_logic      ;
signal fd_f_end4_swb_s1                         : std_logic      ;
signal fd_f_end4_swb_s2                         : std_logic      ;
signal eic_idr_int                              : std_logic_vector(0 downto 0);
signal eic_idr_write_int                        : std_logic      ;
signal eic_ier_int                              : std_logic_vector(0 downto 0);
signal eic_ier_write_int                        : std_logic      ;
signal eic_imr_int                              : std_logic_vector(0 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(0 downto 0);
signal eic_isr_status_int                       : std_logic_vector(0 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(0 downto 0);
signal eic_isr_write_int                        : std_logic      ;
signal fd_rawfifo_empty_int                     : std_logic      ;
signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(5 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal bus_clock_int                            : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_data_i;
  bwsel_reg <= wb_sel_i;
  bus_clock_int <= wb_clk_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      regs_o.rstr_wr_o <= '0';
      fd_gcr_bypass_int <= '0';
      fd_gcr_input_en_int <= '0';
      fd_gcr_csync_int_int <= '0';
      fd_gcr_csync_int_int_delay <= '0';
      fd_gcr_csync_wr_int <= '0';
      fd_gcr_csync_wr_int_delay <= '0';
      fd_gcr_wr_lock_en_int <= '0';
      fd_tar_data_lw <= '0';
      fd_tar_data_lw_delay <= '0';
      fd_tar_data_lw_read_in_progress <= '0';
      fd_tar_data_rwsel <= '0';
      fd_tar_data_int_write <= "0000000000000000000000000000";
      fd_tar_addr_int <= "0000";
      fd_tar_addr_swb <= '0';
      fd_tar_addr_swb_delay <= '0';
      fd_tdcsr_write_int <= '0';
      fd_tdcsr_write_int_delay <= '0';
      fd_tdcsr_read_int <= '0';
      fd_tdcsr_read_int_delay <= '0';
      fd_tdcsr_stop_en_int <= '0';
      fd_tdcsr_stop_en_int_delay <= '0';
      fd_tdcsr_start_dis_int <= '0';
      fd_tdcsr_start_dis_int_delay <= '0';
      fd_tdcsr_start_en_int <= '0';
      fd_tdcsr_start_en_int_delay <= '0';
      fd_tdcsr_stop_dis_int <= '0';
      fd_tdcsr_stop_dis_int_delay <= '0';
      fd_tdcsr_alutrig_int <= '0';
      fd_tdcsr_alutrig_int_delay <= '0';
      fd_calr_cal_pulse_int <= '0';
      fd_calr_cal_pulse_int_delay <= '0';
      fd_calr_psel_int <= "0000";
      fd_calr_psel_swb <= '0';
      fd_calr_psel_swb_delay <= '0';
      fd_adsfr_int <= "000000000000000000";
      fd_adsfr_swb <= '0';
      fd_adsfr_swb_delay <= '0';
      fd_atmcr_c_thr_int <= "0000";
      fd_atmcr_c_thr_swb <= '0';
      fd_atmcr_c_thr_swb_delay <= '0';
      fd_atmcr_f_thr_int <= "00000000000000000000000";
      fd_atmcr_f_thr_swb <= '0';
      fd_atmcr_f_thr_swb_delay <= '0';
      fd_asor_offset_int <= "00000000000000000000000";
      fd_asor_offset_swb <= '0';
      fd_asor_offset_swb_delay <= '0';
      fd_iecraw_lwb <= '0';
      fd_iecraw_lwb_delay <= '0';
      fd_iecraw_lwb_in_progress <= '0';
      fd_iectag_lwb <= '0';
      fd_iectag_lwb_delay <= '0';
      fd_iectag_lwb_in_progress <= '0';
      fd_iepd_rst_stat_int <= '0';
      fd_iepd_rst_stat_int_delay <= '0';
      fd_iepd_pdelay_lwb <= '0';
      fd_iepd_pdelay_lwb_delay <= '0';
      fd_iepd_pdelay_lwb_in_progress <= '0';
      regs_o.scr_data_load_o <= '0';
      fd_scr_sel_dac_int <= '0';
      fd_scr_sel_pll_int <= '0';
      fd_scr_sel_gpio_int <= '0';
      fd_scr_cpol_int <= '0';
      fd_scr_start_int <= '0';
      fd_rcrr_lwb <= '0';
      fd_rcrr_lwb_delay <= '0';
      fd_rcrr_lwb_in_progress <= '0';
      fd_rcfr_lwb <= '0';
      fd_rcfr_lwb_delay <= '0';
      fd_rcfr_lwb_in_progress <= '0';
      fd_tsbcr_enable_int <= '0';
      fd_tsbcr_purge_int <= '0';
      fd_tsbcr_rst_seq_int <= '0';
      fd_tsbcr_rst_seq_int_delay <= '0';
      advance_rbuf_o <= '0';
      fd_dcr1_enable_int <= '0';
      fd_dcr1_mode_int <= '0';
      fd_dcr1_pg_arm_lw <= '0';
      fd_dcr1_pg_arm_lw_delay <= '0';
      fd_dcr1_pg_arm_lw_read_in_progress <= '0';
      fd_dcr1_pg_arm_rwsel <= '0';
      fd_dcr1_pg_arm_int_write <= '0';
      fd_dcr1_update_int <= '0';
      fd_dcr1_update_int_delay <= '0';
      fd_dcr1_force_dly_int <= '0';
      fd_dcr1_force_dly_int_delay <= '0';
      fd_dcr1_pol_int <= '0';
      fd_frr1_int <= "0000000000";
      fd_frr1_swb <= '0';
      fd_frr1_swb_delay <= '0';
      fd_u_start1_int <= "00000000000000000000000000000000";
      fd_u_start1_swb <= '0';
      fd_u_start1_swb_delay <= '0';
      fd_c_start1_int <= "0000000000000000000000000000";
      fd_c_start1_swb <= '0';
      fd_c_start1_swb_delay <= '0';
      fd_f_start1_int <= "000000000000";
      fd_f_start1_swb <= '0';
      fd_f_start1_swb_delay <= '0';
      fd_u_end1_int <= "00000000000000000000000000000000";
      fd_u_end1_swb <= '0';
      fd_u_end1_swb_delay <= '0';
      fd_c_end1_int <= "0000000000000000000000000000";
      fd_c_end1_swb <= '0';
      fd_c_end1_swb_delay <= '0';
      fd_f_end1_int <= "000000000000";
      fd_f_end1_swb <= '0';
      fd_f_end1_swb_delay <= '0';
      fd_dcr2_enable_int <= '0';
      fd_dcr2_mode_int <= '0';
      fd_dcr2_pg_arm_lw <= '0';
      fd_dcr2_pg_arm_lw_delay <= '0';
      fd_dcr2_pg_arm_lw_read_in_progress <= '0';
      fd_dcr2_pg_arm_rwsel <= '0';
      fd_dcr2_pg_arm_int_write <= '0';
      fd_dcr2_update_int <= '0';
      fd_dcr2_update_int_delay <= '0';
      fd_dcr2_force_dly_int <= '0';
      fd_dcr2_force_dly_int_delay <= '0';
      fd_dcr2_pol_int <= '0';
      fd_frr2_int <= "0000000000";
      fd_frr2_swb <= '0';
      fd_frr2_swb_delay <= '0';
      fd_u_start2_int <= "00000000000000000000000000000000";
      fd_u_start2_swb <= '0';
      fd_u_start2_swb_delay <= '0';
      fd_c_start2_int <= "0000000000000000000000000000";
      fd_c_start2_swb <= '0';
      fd_c_start2_swb_delay <= '0';
      fd_f_start2_int <= "000000000000";
      fd_f_start2_swb <= '0';
      fd_f_start2_swb_delay <= '0';
      fd_u_end2_int <= "00000000000000000000000000000000";
      fd_u_end2_swb <= '0';
      fd_u_end2_swb_delay <= '0';
      fd_c_end2_int <= "0000000000000000000000000000";
      fd_c_end2_swb <= '0';
      fd_c_end2_swb_delay <= '0';
      fd_f_end2_int <= "000000000000";
      fd_f_end2_swb <= '0';
      fd_f_end2_swb_delay <= '0';
      fd_dcr3_enable_int <= '0';
      fd_dcr3_mode_int <= '0';
      fd_dcr3_pg_arm_lw <= '0';
      fd_dcr3_pg_arm_lw_delay <= '0';
      fd_dcr3_pg_arm_lw_read_in_progress <= '0';
      fd_dcr3_pg_arm_rwsel <= '0';
      fd_dcr3_pg_arm_int_write <= '0';
      fd_dcr3_update_int <= '0';
      fd_dcr3_update_int_delay <= '0';
      fd_dcr3_force_dly_int <= '0';
      fd_dcr3_force_dly_int_delay <= '0';
      fd_dcr3_pol_int <= '0';
      fd_frr3_int <= "0000000000";
      fd_frr3_swb <= '0';
      fd_frr3_swb_delay <= '0';
      fd_u_start3_int <= "00000000000000000000000000000000";
      fd_u_start3_swb <= '0';
      fd_u_start3_swb_delay <= '0';
      fd_c_start3_int <= "0000000000000000000000000000";
      fd_c_start3_swb <= '0';
      fd_c_start3_swb_delay <= '0';
      fd_f_start3_int <= "000000000000";
      fd_f_start3_swb <= '0';
      fd_f_start3_swb_delay <= '0';
      fd_u_end3_int <= "00000000000000000000000000000000";
      fd_u_end3_swb <= '0';
      fd_u_end3_swb_delay <= '0';
      fd_c_end3_int <= "0000000000000000000000000000";
      fd_c_end3_swb <= '0';
      fd_c_end3_swb_delay <= '0';
      fd_f_end3_int <= "000000000000";
      fd_f_end3_swb <= '0';
      fd_f_end3_swb_delay <= '0';
      fd_dcr4_enable_int <= '0';
      fd_dcr4_mode_int <= '0';
      fd_dcr4_pg_arm_lw <= '0';
      fd_dcr4_pg_arm_lw_delay <= '0';
      fd_dcr4_pg_arm_lw_read_in_progress <= '0';
      fd_dcr4_pg_arm_rwsel <= '0';
      fd_dcr4_pg_arm_int_write <= '0';
      fd_dcr4_update_int <= '0';
      fd_dcr4_update_int_delay <= '0';
      fd_dcr4_force_dly_int <= '0';
      fd_dcr4_force_dly_int_delay <= '0';
      fd_dcr4_pol_int <= '0';
      fd_frr4_int <= "0000000000";
      fd_frr4_swb <= '0';
      fd_frr4_swb_delay <= '0';
      fd_u_start4_int <= "00000000000000000000000000000000";
      fd_u_start4_swb <= '0';
      fd_u_start4_swb_delay <= '0';
      fd_c_start4_int <= "0000000000000000000000000000";
      fd_c_start4_swb <= '0';
      fd_c_start4_swb_delay <= '0';
      fd_f_start4_int <= "000000000000";
      fd_f_start4_swb <= '0';
      fd_f_start4_swb_delay <= '0';
      fd_u_end4_int <= "00000000000000000000000000000000";
      fd_u_end4_swb <= '0';
      fd_u_end4_swb_delay <= '0';
      fd_c_end4_int <= "0000000000000000000000000000";
      fd_c_end4_swb <= '0';
      fd_c_end4_swb_delay <= '0';
      fd_f_end4_int <= "000000000000";
      fd_f_end4_swb <= '0';
      fd_f_end4_swb_delay <= '0';
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
      fd_rawfifo_rdreq_int <= '0';
    elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          regs_o.rstr_wr_o <= '0';
          regs_o.scr_data_load_o <= '0';
          fd_scr_start_int <= '0';
          fd_tsbcr_purge_int <= '0';
          advance_rbuf_o <= '0';
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          ack_in_progress <= '0';
        else
          regs_o.rstr_wr_o <= '0';
          fd_gcr_csync_int_int <= fd_gcr_csync_int_int_delay;
          fd_gcr_csync_int_int_delay <= '0';
          fd_gcr_csync_wr_int <= fd_gcr_csync_wr_int_delay;
          fd_gcr_csync_wr_int_delay <= '0';
          fd_tar_data_lw <= fd_tar_data_lw_delay;
          fd_tar_data_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_tar_data_lw_read_in_progress = '1')) then
            rddata_reg(27 downto 0) <= fd_tar_data_int_read;
            fd_tar_data_lw_read_in_progress <= '0';
          end if;
          fd_tar_addr_swb <= fd_tar_addr_swb_delay;
          fd_tar_addr_swb_delay <= '0';
          fd_tdcsr_write_int <= fd_tdcsr_write_int_delay;
          fd_tdcsr_write_int_delay <= '0';
          fd_tdcsr_read_int <= fd_tdcsr_read_int_delay;
          fd_tdcsr_read_int_delay <= '0';
          fd_tdcsr_stop_en_int <= fd_tdcsr_stop_en_int_delay;
          fd_tdcsr_stop_en_int_delay <= '0';
          fd_tdcsr_start_dis_int <= fd_tdcsr_start_dis_int_delay;
          fd_tdcsr_start_dis_int_delay <= '0';
          fd_tdcsr_start_en_int <= fd_tdcsr_start_en_int_delay;
          fd_tdcsr_start_en_int_delay <= '0';
          fd_tdcsr_stop_dis_int <= fd_tdcsr_stop_dis_int_delay;
          fd_tdcsr_stop_dis_int_delay <= '0';
          fd_tdcsr_alutrig_int <= fd_tdcsr_alutrig_int_delay;
          fd_tdcsr_alutrig_int_delay <= '0';
          fd_calr_cal_pulse_int <= fd_calr_cal_pulse_int_delay;
          fd_calr_cal_pulse_int_delay <= '0';
          fd_calr_psel_swb <= fd_calr_psel_swb_delay;
          fd_calr_psel_swb_delay <= '0';
          fd_adsfr_swb <= fd_adsfr_swb_delay;
          fd_adsfr_swb_delay <= '0';
          fd_atmcr_c_thr_swb <= fd_atmcr_c_thr_swb_delay;
          fd_atmcr_c_thr_swb_delay <= '0';
          fd_atmcr_f_thr_swb <= fd_atmcr_f_thr_swb_delay;
          fd_atmcr_f_thr_swb_delay <= '0';
          fd_asor_offset_swb <= fd_asor_offset_swb_delay;
          fd_asor_offset_swb_delay <= '0';
          fd_iecraw_lwb <= fd_iecraw_lwb_delay;
          fd_iecraw_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_iecraw_lwb_in_progress = '1')) then
            rddata_reg(31 downto 0) <= fd_iecraw_int;
            fd_iecraw_lwb_in_progress <= '0';
          end if;
          fd_iectag_lwb <= fd_iectag_lwb_delay;
          fd_iectag_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_iectag_lwb_in_progress = '1')) then
            rddata_reg(31 downto 0) <= fd_iectag_int;
            fd_iectag_lwb_in_progress <= '0';
          end if;
          fd_iepd_rst_stat_int <= fd_iepd_rst_stat_int_delay;
          fd_iepd_rst_stat_int_delay <= '0';
          fd_iepd_pdelay_lwb <= fd_iepd_pdelay_lwb_delay;
          fd_iepd_pdelay_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_iepd_pdelay_lwb_in_progress = '1')) then
            rddata_reg(8 downto 1) <= fd_iepd_pdelay_int;
            fd_iepd_pdelay_lwb_in_progress <= '0';
          end if;
          regs_o.scr_data_load_o <= '0';
          fd_rcrr_lwb <= fd_rcrr_lwb_delay;
          fd_rcrr_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_rcrr_lwb_in_progress = '1')) then
            rddata_reg(31 downto 0) <= fd_rcrr_int;
            fd_rcrr_lwb_in_progress <= '0';
          end if;
          fd_rcfr_lwb <= fd_rcfr_lwb_delay;
          fd_rcfr_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_rcfr_lwb_in_progress = '1')) then
            rddata_reg(31 downto 0) <= fd_rcfr_int;
            fd_rcfr_lwb_in_progress <= '0';
          end if;
          fd_tsbcr_rst_seq_int <= fd_tsbcr_rst_seq_int_delay;
          fd_tsbcr_rst_seq_int_delay <= '0';
          fd_dcr1_pg_arm_lw <= fd_dcr1_pg_arm_lw_delay;
          fd_dcr1_pg_arm_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_dcr1_pg_arm_lw_read_in_progress = '1')) then
            rddata_reg(2) <= fd_dcr1_pg_arm_int_read;
            fd_dcr1_pg_arm_lw_read_in_progress <= '0';
          end if;
          fd_dcr1_update_int <= fd_dcr1_update_int_delay;
          fd_dcr1_update_int_delay <= '0';
          fd_dcr1_force_dly_int <= fd_dcr1_force_dly_int_delay;
          fd_dcr1_force_dly_int_delay <= '0';
          fd_frr1_swb <= fd_frr1_swb_delay;
          fd_frr1_swb_delay <= '0';
          fd_u_start1_swb <= fd_u_start1_swb_delay;
          fd_u_start1_swb_delay <= '0';
          fd_c_start1_swb <= fd_c_start1_swb_delay;
          fd_c_start1_swb_delay <= '0';
          fd_f_start1_swb <= fd_f_start1_swb_delay;
          fd_f_start1_swb_delay <= '0';
          fd_u_end1_swb <= fd_u_end1_swb_delay;
          fd_u_end1_swb_delay <= '0';
          fd_c_end1_swb <= fd_c_end1_swb_delay;
          fd_c_end1_swb_delay <= '0';
          fd_f_end1_swb <= fd_f_end1_swb_delay;
          fd_f_end1_swb_delay <= '0';
          fd_dcr2_pg_arm_lw <= fd_dcr2_pg_arm_lw_delay;
          fd_dcr2_pg_arm_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_dcr2_pg_arm_lw_read_in_progress = '1')) then
            rddata_reg(2) <= fd_dcr2_pg_arm_int_read;
            fd_dcr2_pg_arm_lw_read_in_progress <= '0';
          end if;
          fd_dcr2_update_int <= fd_dcr2_update_int_delay;
          fd_dcr2_update_int_delay <= '0';
          fd_dcr2_force_dly_int <= fd_dcr2_force_dly_int_delay;
          fd_dcr2_force_dly_int_delay <= '0';
          fd_frr2_swb <= fd_frr2_swb_delay;
          fd_frr2_swb_delay <= '0';
          fd_u_start2_swb <= fd_u_start2_swb_delay;
          fd_u_start2_swb_delay <= '0';
          fd_c_start2_swb <= fd_c_start2_swb_delay;
          fd_c_start2_swb_delay <= '0';
          fd_f_start2_swb <= fd_f_start2_swb_delay;
          fd_f_start2_swb_delay <= '0';
          fd_u_end2_swb <= fd_u_end2_swb_delay;
          fd_u_end2_swb_delay <= '0';
          fd_c_end2_swb <= fd_c_end2_swb_delay;
          fd_c_end2_swb_delay <= '0';
          fd_f_end2_swb <= fd_f_end2_swb_delay;
          fd_f_end2_swb_delay <= '0';
          fd_dcr3_pg_arm_lw <= fd_dcr3_pg_arm_lw_delay;
          fd_dcr3_pg_arm_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_dcr3_pg_arm_lw_read_in_progress = '1')) then
            rddata_reg(2) <= fd_dcr3_pg_arm_int_read;
            fd_dcr3_pg_arm_lw_read_in_progress <= '0';
          end if;
          fd_dcr3_update_int <= fd_dcr3_update_int_delay;
          fd_dcr3_update_int_delay <= '0';
          fd_dcr3_force_dly_int <= fd_dcr3_force_dly_int_delay;
          fd_dcr3_force_dly_int_delay <= '0';
          fd_frr3_swb <= fd_frr3_swb_delay;
          fd_frr3_swb_delay <= '0';
          fd_u_start3_swb <= fd_u_start3_swb_delay;
          fd_u_start3_swb_delay <= '0';
          fd_c_start3_swb <= fd_c_start3_swb_delay;
          fd_c_start3_swb_delay <= '0';
          fd_f_start3_swb <= fd_f_start3_swb_delay;
          fd_f_start3_swb_delay <= '0';
          fd_u_end3_swb <= fd_u_end3_swb_delay;
          fd_u_end3_swb_delay <= '0';
          fd_c_end3_swb <= fd_c_end3_swb_delay;
          fd_c_end3_swb_delay <= '0';
          fd_f_end3_swb <= fd_f_end3_swb_delay;
          fd_f_end3_swb_delay <= '0';
          fd_dcr4_pg_arm_lw <= fd_dcr4_pg_arm_lw_delay;
          fd_dcr4_pg_arm_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (fd_dcr4_pg_arm_lw_read_in_progress = '1')) then
            rddata_reg(2) <= fd_dcr4_pg_arm_int_read;
            fd_dcr4_pg_arm_lw_read_in_progress <= '0';
          end if;
          fd_dcr4_update_int <= fd_dcr4_update_int_delay;
          fd_dcr4_update_int_delay <= '0';
          fd_dcr4_force_dly_int <= fd_dcr4_force_dly_int_delay;
          fd_dcr4_force_dly_int_delay <= '0';
          fd_frr4_swb <= fd_frr4_swb_delay;
          fd_frr4_swb_delay <= '0';
          fd_u_start4_swb <= fd_u_start4_swb_delay;
          fd_u_start4_swb_delay <= '0';
          fd_c_start4_swb <= fd_c_start4_swb_delay;
          fd_c_start4_swb_delay <= '0';
          fd_f_start4_swb <= fd_f_start4_swb_delay;
          fd_f_start4_swb_delay <= '0';
          fd_u_end4_swb <= fd_u_end4_swb_delay;
          fd_u_end4_swb_delay <= '0';
          fd_c_end4_swb <= fd_c_end4_swb_delay;
          fd_c_end4_swb_delay <= '0';
          fd_f_end4_swb <= fd_f_end4_swb_delay;
          fd_f_end4_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(5 downto 0) is
          when "000000" => 
            if (wb_we_i = '1') then
              regs_o.rstr_wr_o <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000001" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= "11110001100111101101111000011010";
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000010" => 
            if (wb_we_i = '1') then
              fd_gcr_bypass_int <= wrdata_reg(0);
              rddata_reg(0) <= 'X';
              fd_gcr_input_en_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_gcr_csync_int_int <= wrdata_reg(2);
              fd_gcr_csync_int_int_delay <= wrdata_reg(2);
              rddata_reg(3) <= 'X';
              fd_gcr_csync_wr_int <= wrdata_reg(3);
              fd_gcr_csync_wr_int_delay <= wrdata_reg(3);
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              fd_gcr_wr_lock_en_int <= wrdata_reg(5);
              rddata_reg(6) <= 'X';
            else
              rddata_reg(0) <= fd_gcr_bypass_int;
              rddata_reg(1) <= fd_gcr_input_en_int;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= regs_i.gcr_wr_ready_i;
              rddata_reg(5) <= fd_gcr_wr_lock_en_int;
              rddata_reg(6) <= regs_i.gcr_wr_locked_i;
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "000011" => 
            if (wb_we_i = '1') then
              fd_tar_data_int_write <= wrdata_reg(27 downto 0);
              fd_tar_data_lw <= '1';
              fd_tar_data_lw_delay <= '1';
              fd_tar_data_lw_read_in_progress <= '0';
              fd_tar_data_rwsel <= '1';
              fd_tar_addr_int <= wrdata_reg(31 downto 28);
              fd_tar_addr_swb <= '1';
              fd_tar_addr_swb_delay <= '1';
            else
              fd_tar_data_lw <= '1';
              fd_tar_data_lw_delay <= '1';
              fd_tar_data_lw_read_in_progress <= '1';
              fd_tar_data_rwsel <= '0';
              rddata_reg(31 downto 28) <= fd_tar_addr_int;
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "000100" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              fd_tdcsr_write_int <= wrdata_reg(0);
              fd_tdcsr_write_int_delay <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              fd_tdcsr_read_int <= wrdata_reg(1);
              fd_tdcsr_read_int_delay <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              fd_tdcsr_stop_en_int <= wrdata_reg(6);
              fd_tdcsr_stop_en_int_delay <= wrdata_reg(6);
              rddata_reg(7) <= 'X';
              fd_tdcsr_start_dis_int <= wrdata_reg(7);
              fd_tdcsr_start_dis_int_delay <= wrdata_reg(7);
              rddata_reg(8) <= 'X';
              fd_tdcsr_start_en_int <= wrdata_reg(8);
              fd_tdcsr_start_en_int_delay <= wrdata_reg(8);
              rddata_reg(9) <= 'X';
              fd_tdcsr_stop_dis_int <= wrdata_reg(9);
              fd_tdcsr_stop_dis_int_delay <= wrdata_reg(9);
              rddata_reg(10) <= 'X';
              fd_tdcsr_alutrig_int <= wrdata_reg(10);
              fd_tdcsr_alutrig_int_delay <= wrdata_reg(10);
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= fd_tdcsr_err_sync1;
              rddata_reg(3) <= fd_tdcsr_int_sync1;
              rddata_reg(4) <= fd_tdcsr_load_sync1;
              rddata_reg(5) <= fd_tdcsr_empty_sync1;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "000101" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              fd_calr_cal_pulse_int <= wrdata_reg(0);
              fd_calr_cal_pulse_int_delay <= wrdata_reg(0);
              fd_calr_psel_int <= wrdata_reg(4 downto 1);
              fd_calr_psel_swb <= '1';
              fd_calr_psel_swb_delay <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(4 downto 1) <= fd_calr_psel_int;
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "000110" => 
            if (wb_we_i = '1') then
              fd_adsfr_int <= wrdata_reg(17 downto 0);
              fd_adsfr_swb <= '1';
              fd_adsfr_swb_delay <= '1';
            else
              rddata_reg(17 downto 0) <= fd_adsfr_int;
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "000111" => 
            if (wb_we_i = '1') then
              fd_atmcr_c_thr_int <= wrdata_reg(3 downto 0);
              fd_atmcr_c_thr_swb <= '1';
              fd_atmcr_c_thr_swb_delay <= '1';
              fd_atmcr_f_thr_int <= wrdata_reg(26 downto 4);
              fd_atmcr_f_thr_swb <= '1';
              fd_atmcr_f_thr_swb_delay <= '1';
            else
              rddata_reg(3 downto 0) <= fd_atmcr_c_thr_int;
              rddata_reg(26 downto 4) <= fd_atmcr_f_thr_int;
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001000" => 
            if (wb_we_i = '1') then
              fd_asor_offset_int <= wrdata_reg(22 downto 0);
              fd_asor_offset_swb <= '1';
              fd_asor_offset_swb_delay <= '1';
            else
              rddata_reg(22 downto 0) <= fd_asor_offset_int;
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001001" => 
            if (wb_we_i = '1') then
            else
              fd_iecraw_lwb <= '1';
              fd_iecraw_lwb_delay <= '1';
              fd_iecraw_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "001010" => 
            if (wb_we_i = '1') then
            else
              fd_iectag_lwb <= '1';
              fd_iectag_lwb_delay <= '1';
              fd_iectag_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "001011" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              fd_iepd_rst_stat_int <= wrdata_reg(0);
              fd_iepd_rst_stat_int_delay <= wrdata_reg(0);
            else
              rddata_reg(0) <= 'X';
              fd_iepd_pdelay_lwb <= '1';
              fd_iepd_pdelay_lwb_delay <= '1';
              fd_iepd_pdelay_lwb_in_progress <= '1';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "001100" => 
            if (wb_we_i = '1') then
              regs_o.scr_data_load_o <= '1';
              rddata_reg(24) <= 'X';
              fd_scr_sel_dac_int <= wrdata_reg(24);
              rddata_reg(25) <= 'X';
              fd_scr_sel_pll_int <= wrdata_reg(25);
              rddata_reg(26) <= 'X';
              fd_scr_sel_gpio_int <= wrdata_reg(26);
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              fd_scr_cpol_int <= wrdata_reg(28);
              fd_scr_start_int <= wrdata_reg(29);
              rddata_reg(29) <= 'X';
            else
              rddata_reg(23 downto 0) <= regs_i.scr_data_i;
              rddata_reg(24) <= fd_scr_sel_dac_int;
              rddata_reg(25) <= fd_scr_sel_pll_int;
              rddata_reg(26) <= fd_scr_sel_gpio_int;
              rddata_reg(27) <= regs_i.scr_ready_i;
              rddata_reg(28) <= fd_scr_cpol_int;
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "001101" => 
            if (wb_we_i = '1') then
            else
              fd_rcrr_lwb <= '1';
              fd_rcrr_lwb_delay <= '1';
              fd_rcrr_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "001110" => 
            if (wb_we_i = '1') then
            else
              fd_rcfr_lwb <= '1';
              fd_rcfr_lwb_delay <= '1';
              fd_rcfr_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "001111" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              fd_tsbcr_enable_int <= wrdata_reg(0);
              fd_tsbcr_purge_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_tsbcr_rst_seq_int <= wrdata_reg(2);
              fd_tsbcr_rst_seq_int_delay <= wrdata_reg(2);
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
            else
              rddata_reg(0) <= fd_tsbcr_enable_int;
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= regs_i.tsbcr_full_i;
              rddata_reg(4) <= regs_i.tsbcr_empty_i;
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "010000" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= regs_i.tsbr_u_i;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010001" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(27 downto 0) <= regs_i.tsbr_c_i;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010010" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(11 downto 0) <= regs_i.tsbr_fid_fine_i;
              rddata_reg(31 downto 16) <= regs_i.tsbr_fid_seqid_i;
              advance_rbuf_o <= '1';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011000" => 
            if (wb_we_i = '1') then
              fd_dcr1_enable_int <= wrdata_reg(0);
              rddata_reg(0) <= 'X';
              fd_dcr1_mode_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_dcr1_pg_arm_int_write <= wrdata_reg(2);
              fd_dcr1_pg_arm_lw <= '1';
              fd_dcr1_pg_arm_lw_delay <= '1';
              fd_dcr1_pg_arm_lw_read_in_progress <= '0';
              fd_dcr1_pg_arm_rwsel <= '1';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              fd_dcr1_update_int <= wrdata_reg(4);
              fd_dcr1_update_int_delay <= wrdata_reg(4);
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              fd_dcr1_force_dly_int <= wrdata_reg(6);
              fd_dcr1_force_dly_int_delay <= wrdata_reg(6);
              fd_dcr1_pol_int <= wrdata_reg(7);
              rddata_reg(7) <= 'X';
            else
              rddata_reg(0) <= fd_dcr1_enable_int;
              rddata_reg(1) <= fd_dcr1_mode_int;
              rddata_reg(2) <= 'X';
              fd_dcr1_pg_arm_lw <= '1';
              fd_dcr1_pg_arm_lw_delay <= '1';
              fd_dcr1_pg_arm_lw_read_in_progress <= '1';
              fd_dcr1_pg_arm_rwsel <= '0';
              rddata_reg(3) <= fd_dcr1_pg_trig_sync1;
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= fd_dcr1_upd_done_sync1;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= fd_dcr1_pol_int;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "011001" => 
            if (wb_we_i = '1') then
              fd_frr1_int <= wrdata_reg(9 downto 0);
              fd_frr1_swb <= '1';
              fd_frr1_swb_delay <= '1';
            else
              rddata_reg(9 downto 0) <= fd_frr1_int;
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011010" => 
            if (wb_we_i = '1') then
              fd_u_start1_int <= wrdata_reg(31 downto 0);
              fd_u_start1_swb <= '1';
              fd_u_start1_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_start1_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011011" => 
            if (wb_we_i = '1') then
              fd_c_start1_int <= wrdata_reg(27 downto 0);
              fd_c_start1_swb <= '1';
              fd_c_start1_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_start1_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011100" => 
            if (wb_we_i = '1') then
              fd_f_start1_int <= wrdata_reg(11 downto 0);
              fd_f_start1_swb <= '1';
              fd_f_start1_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_start1_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011101" => 
            if (wb_we_i = '1') then
              fd_u_end1_int <= wrdata_reg(31 downto 0);
              fd_u_end1_swb <= '1';
              fd_u_end1_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_end1_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011110" => 
            if (wb_we_i = '1') then
              fd_c_end1_int <= wrdata_reg(27 downto 0);
              fd_c_end1_swb <= '1';
              fd_c_end1_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_end1_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011111" => 
            if (wb_we_i = '1') then
              fd_f_end1_int <= wrdata_reg(11 downto 0);
              fd_f_end1_swb <= '1';
              fd_f_end1_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_end1_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100000" => 
            if (wb_we_i = '1') then
              fd_dcr2_enable_int <= wrdata_reg(0);
              rddata_reg(0) <= 'X';
              fd_dcr2_mode_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_dcr2_pg_arm_int_write <= wrdata_reg(2);
              fd_dcr2_pg_arm_lw <= '1';
              fd_dcr2_pg_arm_lw_delay <= '1';
              fd_dcr2_pg_arm_lw_read_in_progress <= '0';
              fd_dcr2_pg_arm_rwsel <= '1';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              fd_dcr2_update_int <= wrdata_reg(4);
              fd_dcr2_update_int_delay <= wrdata_reg(4);
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              fd_dcr2_force_dly_int <= wrdata_reg(6);
              fd_dcr2_force_dly_int_delay <= wrdata_reg(6);
              fd_dcr2_pol_int <= wrdata_reg(7);
              rddata_reg(7) <= 'X';
            else
              rddata_reg(0) <= fd_dcr2_enable_int;
              rddata_reg(1) <= fd_dcr2_mode_int;
              rddata_reg(2) <= 'X';
              fd_dcr2_pg_arm_lw <= '1';
              fd_dcr2_pg_arm_lw_delay <= '1';
              fd_dcr2_pg_arm_lw_read_in_progress <= '1';
              fd_dcr2_pg_arm_rwsel <= '0';
              rddata_reg(3) <= fd_dcr2_pg_trig_sync1;
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= fd_dcr2_upd_done_sync1;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= fd_dcr2_pol_int;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "100001" => 
            if (wb_we_i = '1') then
              fd_frr2_int <= wrdata_reg(9 downto 0);
              fd_frr2_swb <= '1';
              fd_frr2_swb_delay <= '1';
            else
              rddata_reg(9 downto 0) <= fd_frr2_int;
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100010" => 
            if (wb_we_i = '1') then
              fd_u_start2_int <= wrdata_reg(31 downto 0);
              fd_u_start2_swb <= '1';
              fd_u_start2_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_start2_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100011" => 
            if (wb_we_i = '1') then
              fd_c_start2_int <= wrdata_reg(27 downto 0);
              fd_c_start2_swb <= '1';
              fd_c_start2_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_start2_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100100" => 
            if (wb_we_i = '1') then
              fd_f_start2_int <= wrdata_reg(11 downto 0);
              fd_f_start2_swb <= '1';
              fd_f_start2_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_start2_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100101" => 
            if (wb_we_i = '1') then
              fd_u_end2_int <= wrdata_reg(31 downto 0);
              fd_u_end2_swb <= '1';
              fd_u_end2_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_end2_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100110" => 
            if (wb_we_i = '1') then
              fd_c_end2_int <= wrdata_reg(27 downto 0);
              fd_c_end2_swb <= '1';
              fd_c_end2_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_end2_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100111" => 
            if (wb_we_i = '1') then
              fd_f_end2_int <= wrdata_reg(11 downto 0);
              fd_f_end2_swb <= '1';
              fd_f_end2_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_end2_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101000" => 
            if (wb_we_i = '1') then
              fd_dcr3_enable_int <= wrdata_reg(0);
              rddata_reg(0) <= 'X';
              fd_dcr3_mode_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_dcr3_pg_arm_int_write <= wrdata_reg(2);
              fd_dcr3_pg_arm_lw <= '1';
              fd_dcr3_pg_arm_lw_delay <= '1';
              fd_dcr3_pg_arm_lw_read_in_progress <= '0';
              fd_dcr3_pg_arm_rwsel <= '1';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              fd_dcr3_update_int <= wrdata_reg(4);
              fd_dcr3_update_int_delay <= wrdata_reg(4);
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              fd_dcr3_force_dly_int <= wrdata_reg(6);
              fd_dcr3_force_dly_int_delay <= wrdata_reg(6);
              fd_dcr3_pol_int <= wrdata_reg(7);
              rddata_reg(7) <= 'X';
            else
              rddata_reg(0) <= fd_dcr3_enable_int;
              rddata_reg(1) <= fd_dcr3_mode_int;
              rddata_reg(2) <= 'X';
              fd_dcr3_pg_arm_lw <= '1';
              fd_dcr3_pg_arm_lw_delay <= '1';
              fd_dcr3_pg_arm_lw_read_in_progress <= '1';
              fd_dcr3_pg_arm_rwsel <= '0';
              rddata_reg(3) <= fd_dcr3_pg_trig_sync1;
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= fd_dcr3_upd_done_sync1;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= fd_dcr3_pol_int;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "101001" => 
            if (wb_we_i = '1') then
              fd_frr3_int <= wrdata_reg(9 downto 0);
              fd_frr3_swb <= '1';
              fd_frr3_swb_delay <= '1';
            else
              rddata_reg(9 downto 0) <= fd_frr3_int;
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101010" => 
            if (wb_we_i = '1') then
              fd_u_start3_int <= wrdata_reg(31 downto 0);
              fd_u_start3_swb <= '1';
              fd_u_start3_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_start3_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101011" => 
            if (wb_we_i = '1') then
              fd_c_start3_int <= wrdata_reg(27 downto 0);
              fd_c_start3_swb <= '1';
              fd_c_start3_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_start3_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101100" => 
            if (wb_we_i = '1') then
              fd_f_start3_int <= wrdata_reg(11 downto 0);
              fd_f_start3_swb <= '1';
              fd_f_start3_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_start3_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101101" => 
            if (wb_we_i = '1') then
              fd_u_end3_int <= wrdata_reg(31 downto 0);
              fd_u_end3_swb <= '1';
              fd_u_end3_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_end3_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101110" => 
            if (wb_we_i = '1') then
              fd_c_end3_int <= wrdata_reg(27 downto 0);
              fd_c_end3_swb <= '1';
              fd_c_end3_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_end3_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101111" => 
            if (wb_we_i = '1') then
              fd_f_end3_int <= wrdata_reg(11 downto 0);
              fd_f_end3_swb <= '1';
              fd_f_end3_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_end3_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110000" => 
            if (wb_we_i = '1') then
              fd_dcr4_enable_int <= wrdata_reg(0);
              rddata_reg(0) <= 'X';
              fd_dcr4_mode_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              fd_dcr4_pg_arm_int_write <= wrdata_reg(2);
              fd_dcr4_pg_arm_lw <= '1';
              fd_dcr4_pg_arm_lw_delay <= '1';
              fd_dcr4_pg_arm_lw_read_in_progress <= '0';
              fd_dcr4_pg_arm_rwsel <= '1';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              fd_dcr4_update_int <= wrdata_reg(4);
              fd_dcr4_update_int_delay <= wrdata_reg(4);
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              fd_dcr4_force_dly_int <= wrdata_reg(6);
              fd_dcr4_force_dly_int_delay <= wrdata_reg(6);
              fd_dcr4_pol_int <= wrdata_reg(7);
              rddata_reg(7) <= 'X';
            else
              rddata_reg(0) <= fd_dcr4_enable_int;
              rddata_reg(1) <= fd_dcr4_mode_int;
              rddata_reg(2) <= 'X';
              fd_dcr4_pg_arm_lw <= '1';
              fd_dcr4_pg_arm_lw_delay <= '1';
              fd_dcr4_pg_arm_lw_read_in_progress <= '1';
              fd_dcr4_pg_arm_rwsel <= '0';
              rddata_reg(3) <= fd_dcr4_pg_trig_sync1;
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= fd_dcr4_upd_done_sync1;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= fd_dcr4_pol_int;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "110001" => 
            if (wb_we_i = '1') then
              fd_frr4_int <= wrdata_reg(9 downto 0);
              fd_frr4_swb <= '1';
              fd_frr4_swb_delay <= '1';
            else
              rddata_reg(9 downto 0) <= fd_frr4_int;
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110010" => 
            if (wb_we_i = '1') then
              fd_u_start4_int <= wrdata_reg(31 downto 0);
              fd_u_start4_swb <= '1';
              fd_u_start4_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_start4_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110011" => 
            if (wb_we_i = '1') then
              fd_c_start4_int <= wrdata_reg(27 downto 0);
              fd_c_start4_swb <= '1';
              fd_c_start4_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_start4_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110100" => 
            if (wb_we_i = '1') then
              fd_f_start4_int <= wrdata_reg(11 downto 0);
              fd_f_start4_swb <= '1';
              fd_f_start4_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_start4_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110101" => 
            if (wb_we_i = '1') then
              fd_u_end4_int <= wrdata_reg(31 downto 0);
              fd_u_end4_swb <= '1';
              fd_u_end4_swb_delay <= '1';
            else
              rddata_reg(31 downto 0) <= fd_u_end4_int;
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110110" => 
            if (wb_we_i = '1') then
              fd_c_end4_int <= wrdata_reg(27 downto 0);
              fd_c_end4_swb <= '1';
              fd_c_end4_swb_delay <= '1';
            else
              rddata_reg(27 downto 0) <= fd_c_end4_int;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "110111" => 
            if (wb_we_i = '1') then
              fd_f_end4_int <= wrdata_reg(11 downto 0);
              fd_f_end4_swb <= '1';
              fd_f_end4_swb_delay <= '1';
            else
              rddata_reg(11 downto 0) <= fd_f_end4_int;
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "111000" => 
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "111001" => 
            if (wb_we_i = '1') then
              eic_ier_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "111010" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(0) <= eic_imr_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "111011" => 
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            else
              rddata_reg(0) <= eic_isr_status_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "111100" => 
            if (wb_we_i = '1') then
            else
              if (fd_rawfifo_rdreq_int_d0 = '0') then
                fd_rawfifo_rdreq_int <= not fd_rawfifo_rdreq_int;
              else
                rddata_reg(27 downto 0) <= fd_rawfifo_out_int(27 downto 0);
                ack_in_progress <= '1';
                ack_sreg(0) <= '1';
              end if;
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
          when "111101" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(27 downto 0) <= fd_rawfifo_out_int(55 downto 28);
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "111110" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(17) <= fd_rawfifo_empty_int;
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_data_o <= rddata_reg;
-- Reset trigger
-- pass-through field: Reset trigger in register: Reset Register
  regs_o.rstr_o <= wrdata_reg(31 downto 0);
-- Bypass delay block
-- synchronizer chain for field : Bypass delay block (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.gcr_bypass_o <= '0';
      fd_gcr_bypass_sync0 <= '0';
      fd_gcr_bypass_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_gcr_bypass_sync0 <= fd_gcr_bypass_int;
      fd_gcr_bypass_sync1 <= fd_gcr_bypass_sync0;
      regs_o.gcr_bypass_o <= fd_gcr_bypass_sync1;
    end if;
  end process;
  
  
-- Enable trigger input
-- synchronizer chain for field : Enable trigger input (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.gcr_input_en_o <= '0';
      fd_gcr_input_en_sync0 <= '0';
      fd_gcr_input_en_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_gcr_input_en_sync0 <= fd_gcr_input_en_int;
      fd_gcr_input_en_sync1 <= fd_gcr_input_en_sync0;
      regs_o.gcr_input_en_o <= fd_gcr_input_en_sync1;
    end if;
  end process;
  
  
-- Internal Counter Sync
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.gcr_csync_int_o <= '0';
      fd_gcr_csync_int_sync0 <= '0';
      fd_gcr_csync_int_sync1 <= '0';
      fd_gcr_csync_int_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_gcr_csync_int_sync0 <= fd_gcr_csync_int_int;
      fd_gcr_csync_int_sync1 <= fd_gcr_csync_int_sync0;
      fd_gcr_csync_int_sync2 <= fd_gcr_csync_int_sync1;
      regs_o.gcr_csync_int_o <= fd_gcr_csync_int_sync2 and (not fd_gcr_csync_int_sync1);
    end if;
  end process;
  
  
-- White Rabbit Counter Sync
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.gcr_csync_wr_o <= '0';
      fd_gcr_csync_wr_sync0 <= '0';
      fd_gcr_csync_wr_sync1 <= '0';
      fd_gcr_csync_wr_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_gcr_csync_wr_sync0 <= fd_gcr_csync_wr_int;
      fd_gcr_csync_wr_sync1 <= fd_gcr_csync_wr_sync0;
      fd_gcr_csync_wr_sync2 <= fd_gcr_csync_wr_sync1;
      regs_o.gcr_csync_wr_o <= fd_gcr_csync_wr_sync2 and (not fd_gcr_csync_wr_sync1);
    end if;
  end process;
  
  
-- White Rabbit Timecode Ready
-- White Rabbit Locking Enable
  regs_o.gcr_wr_lock_en_o <= fd_gcr_wr_lock_en_int;
-- White Rabbit Oscillator Locked
-- DATA
-- asynchronous std_logic_vector register : DATA (type RW/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tar_data_lw_s0 <= '0';
      fd_tar_data_lw_s1 <= '0';
      fd_tar_data_lw_s2 <= '0';
      regs_o.tar_data_o <= "0000000000000000000000000000";
      regs_o.tar_data_load_o <= '0';
      fd_tar_data_int_read <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_tar_data_lw_s0 <= fd_tar_data_lw;
      fd_tar_data_lw_s1 <= fd_tar_data_lw_s0;
      fd_tar_data_lw_s2 <= fd_tar_data_lw_s1;
      if ((fd_tar_data_lw_s2 = '0') and (fd_tar_data_lw_s1 = '1')) then
        if (fd_tar_data_rwsel = '1') then
          regs_o.tar_data_o <= fd_tar_data_int_write;
          regs_o.tar_data_load_o <= '1';
        else
          regs_o.tar_data_load_o <= '0';
          fd_tar_data_int_read <= regs_i.tar_data_i;
        end if;
      else
        regs_o.tar_data_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- ADDR
-- asynchronous std_logic_vector register : ADDR (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tar_addr_swb_s0 <= '0';
      fd_tar_addr_swb_s1 <= '0';
      fd_tar_addr_swb_s2 <= '0';
      regs_o.tar_addr_o <= "0000";
    elsif rising_edge(clk_ref_i) then
      fd_tar_addr_swb_s0 <= fd_tar_addr_swb;
      fd_tar_addr_swb_s1 <= fd_tar_addr_swb_s0;
      fd_tar_addr_swb_s2 <= fd_tar_addr_swb_s1;
      if ((fd_tar_addr_swb_s2 = '0') and (fd_tar_addr_swb_s1 = '1')) then
        regs_o.tar_addr_o <= fd_tar_addr_int;
      end if;
    end if;
  end process;
  
  
-- Start TDC write
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_write_o <= '0';
      fd_tdcsr_write_sync0 <= '0';
      fd_tdcsr_write_sync1 <= '0';
      fd_tdcsr_write_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_write_sync0 <= fd_tdcsr_write_int;
      fd_tdcsr_write_sync1 <= fd_tdcsr_write_sync0;
      fd_tdcsr_write_sync2 <= fd_tdcsr_write_sync1;
      regs_o.tdcsr_write_o <= fd_tdcsr_write_sync2 and (not fd_tdcsr_write_sync1);
    end if;
  end process;
  
  
-- Start TDC read
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_read_o <= '0';
      fd_tdcsr_read_sync0 <= '0';
      fd_tdcsr_read_sync1 <= '0';
      fd_tdcsr_read_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_read_sync0 <= fd_tdcsr_read_int;
      fd_tdcsr_read_sync1 <= fd_tdcsr_read_sync0;
      fd_tdcsr_read_sync2 <= fd_tdcsr_read_sync1;
      regs_o.tdcsr_read_o <= fd_tdcsr_read_sync2 and (not fd_tdcsr_read_sync1);
    end if;
  end process;
  
  
-- Error flag
-- synchronizer chain for field : Error flag (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tdcsr_err_sync0 <= '0';
      fd_tdcsr_err_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_err_sync0 <= regs_i.tdcsr_err_i;
      fd_tdcsr_err_sync1 <= fd_tdcsr_err_sync0;
    end if;
  end process;
  
  
-- Interrupt flag
-- synchronizer chain for field : Interrupt flag (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tdcsr_int_sync0 <= '0';
      fd_tdcsr_int_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_int_sync0 <= regs_i.tdcsr_int_i;
      fd_tdcsr_int_sync1 <= fd_tdcsr_int_sync0;
    end if;
  end process;
  
  
-- Load flag
-- synchronizer chain for field : Load flag (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tdcsr_load_sync0 <= '0';
      fd_tdcsr_load_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_load_sync0 <= regs_i.tdcsr_load_i;
      fd_tdcsr_load_sync1 <= fd_tdcsr_load_sync0;
    end if;
  end process;
  
  
-- Empty flag
-- synchronizer chain for field : Empty flag (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tdcsr_empty_sync0 <= '0';
      fd_tdcsr_empty_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_empty_sync0 <= regs_i.tdcsr_empty_i;
      fd_tdcsr_empty_sync1 <= fd_tdcsr_empty_sync0;
    end if;
  end process;
  
  
-- Start enable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_stop_en_o <= '0';
      fd_tdcsr_stop_en_sync0 <= '0';
      fd_tdcsr_stop_en_sync1 <= '0';
      fd_tdcsr_stop_en_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_stop_en_sync0 <= fd_tdcsr_stop_en_int;
      fd_tdcsr_stop_en_sync1 <= fd_tdcsr_stop_en_sync0;
      fd_tdcsr_stop_en_sync2 <= fd_tdcsr_stop_en_sync1;
      regs_o.tdcsr_stop_en_o <= fd_tdcsr_stop_en_sync2 and (not fd_tdcsr_stop_en_sync1);
    end if;
  end process;
  
  
-- Start disable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_start_dis_o <= '0';
      fd_tdcsr_start_dis_sync0 <= '0';
      fd_tdcsr_start_dis_sync1 <= '0';
      fd_tdcsr_start_dis_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_start_dis_sync0 <= fd_tdcsr_start_dis_int;
      fd_tdcsr_start_dis_sync1 <= fd_tdcsr_start_dis_sync0;
      fd_tdcsr_start_dis_sync2 <= fd_tdcsr_start_dis_sync1;
      regs_o.tdcsr_start_dis_o <= fd_tdcsr_start_dis_sync2 and (not fd_tdcsr_start_dis_sync1);
    end if;
  end process;
  
  
-- Stop enable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_start_en_o <= '0';
      fd_tdcsr_start_en_sync0 <= '0';
      fd_tdcsr_start_en_sync1 <= '0';
      fd_tdcsr_start_en_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_start_en_sync0 <= fd_tdcsr_start_en_int;
      fd_tdcsr_start_en_sync1 <= fd_tdcsr_start_en_sync0;
      fd_tdcsr_start_en_sync2 <= fd_tdcsr_start_en_sync1;
      regs_o.tdcsr_start_en_o <= fd_tdcsr_start_en_sync2 and (not fd_tdcsr_start_en_sync1);
    end if;
  end process;
  
  
-- Stop disable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_stop_dis_o <= '0';
      fd_tdcsr_stop_dis_sync0 <= '0';
      fd_tdcsr_stop_dis_sync1 <= '0';
      fd_tdcsr_stop_dis_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_stop_dis_sync0 <= fd_tdcsr_stop_dis_int;
      fd_tdcsr_stop_dis_sync1 <= fd_tdcsr_stop_dis_sync0;
      fd_tdcsr_stop_dis_sync2 <= fd_tdcsr_stop_dis_sync1;
      regs_o.tdcsr_stop_dis_o <= fd_tdcsr_stop_dis_sync2 and (not fd_tdcsr_stop_dis_sync1);
    end if;
  end process;
  
  
-- write 1: Pulse the Alutrigger line
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tdcsr_alutrig_o <= '0';
      fd_tdcsr_alutrig_sync0 <= '0';
      fd_tdcsr_alutrig_sync1 <= '0';
      fd_tdcsr_alutrig_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tdcsr_alutrig_sync0 <= fd_tdcsr_alutrig_int;
      fd_tdcsr_alutrig_sync1 <= fd_tdcsr_alutrig_sync0;
      fd_tdcsr_alutrig_sync2 <= fd_tdcsr_alutrig_sync1;
      regs_o.tdcsr_alutrig_o <= fd_tdcsr_alutrig_sync2 and (not fd_tdcsr_alutrig_sync1);
    end if;
  end process;
  
  
-- Triggers calibration pulses
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.calr_cal_pulse_o <= '0';
      fd_calr_cal_pulse_sync0 <= '0';
      fd_calr_cal_pulse_sync1 <= '0';
      fd_calr_cal_pulse_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_calr_cal_pulse_sync0 <= fd_calr_cal_pulse_int;
      fd_calr_cal_pulse_sync1 <= fd_calr_cal_pulse_sync0;
      fd_calr_cal_pulse_sync2 <= fd_calr_cal_pulse_sync1;
      regs_o.calr_cal_pulse_o <= fd_calr_cal_pulse_sync2 and (not fd_calr_cal_pulse_sync1);
    end if;
  end process;
  
  
-- Enable pulse generation
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_calr_psel_swb_s0 <= '0';
      fd_calr_psel_swb_s1 <= '0';
      fd_calr_psel_swb_s2 <= '0';
      regs_o.calr_psel_o <= "0000";
    elsif rising_edge(clk_ref_i) then
      fd_calr_psel_swb_s0 <= fd_calr_psel_swb;
      fd_calr_psel_swb_s1 <= fd_calr_psel_swb_s0;
      fd_calr_psel_swb_s2 <= fd_calr_psel_swb_s1;
      if ((fd_calr_psel_swb_s2 = '0') and (fd_calr_psel_swb_s1 = '1')) then
        regs_o.calr_psel_o <= fd_calr_psel_int;
      end if;
    end if;
  end process;
  
  
-- ADFSR Value
-- asynchronous std_logic_vector register : ADFSR Value (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_adsfr_swb_s0 <= '0';
      fd_adsfr_swb_s1 <= '0';
      fd_adsfr_swb_s2 <= '0';
      regs_o.adsfr_o <= "000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_adsfr_swb_s0 <= fd_adsfr_swb;
      fd_adsfr_swb_s1 <= fd_adsfr_swb_s0;
      fd_adsfr_swb_s2 <= fd_adsfr_swb_s1;
      if ((fd_adsfr_swb_s2 = '0') and (fd_adsfr_swb_s1 = '1')) then
        regs_o.adsfr_o <= fd_adsfr_int;
      end if;
    end if;
  end process;
  
  
-- Wraparound Coarse Threshold
-- asynchronous std_logic_vector register : Wraparound Coarse Threshold (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_atmcr_c_thr_swb_s0 <= '0';
      fd_atmcr_c_thr_swb_s1 <= '0';
      fd_atmcr_c_thr_swb_s2 <= '0';
      regs_o.atmcr_c_thr_o <= "0000";
    elsif rising_edge(clk_ref_i) then
      fd_atmcr_c_thr_swb_s0 <= fd_atmcr_c_thr_swb;
      fd_atmcr_c_thr_swb_s1 <= fd_atmcr_c_thr_swb_s0;
      fd_atmcr_c_thr_swb_s2 <= fd_atmcr_c_thr_swb_s1;
      if ((fd_atmcr_c_thr_swb_s2 = '0') and (fd_atmcr_c_thr_swb_s1 = '1')) then
        regs_o.atmcr_c_thr_o <= fd_atmcr_c_thr_int;
      end if;
    end if;
  end process;
  
  
-- Wraparound Fine Threshold
-- asynchronous std_logic_vector register : Wraparound Fine Threshold (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_atmcr_f_thr_swb_s0 <= '0';
      fd_atmcr_f_thr_swb_s1 <= '0';
      fd_atmcr_f_thr_swb_s2 <= '0';
      regs_o.atmcr_f_thr_o <= "00000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_atmcr_f_thr_swb_s0 <= fd_atmcr_f_thr_swb;
      fd_atmcr_f_thr_swb_s1 <= fd_atmcr_f_thr_swb_s0;
      fd_atmcr_f_thr_swb_s2 <= fd_atmcr_f_thr_swb_s1;
      if ((fd_atmcr_f_thr_swb_s2 = '0') and (fd_atmcr_f_thr_swb_s1 = '1')) then
        regs_o.atmcr_f_thr_o <= fd_atmcr_f_thr_int;
      end if;
    end if;
  end process;
  
  
-- Start Offset
-- asynchronous std_logic_vector register : Start Offset (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_asor_offset_swb_s0 <= '0';
      fd_asor_offset_swb_s1 <= '0';
      fd_asor_offset_swb_s2 <= '0';
      regs_o.asor_offset_o <= "00000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_asor_offset_swb_s0 <= fd_asor_offset_swb;
      fd_asor_offset_swb_s1 <= fd_asor_offset_swb_s0;
      fd_asor_offset_swb_s2 <= fd_asor_offset_swb_s1;
      if ((fd_asor_offset_swb_s2 = '0') and (fd_asor_offset_swb_s1 = '1')) then
        regs_o.asor_offset_o <= fd_asor_offset_int;
      end if;
    end if;
  end process;
  
  
-- Number of raw events
-- asynchronous std_logic_vector register : Number of raw events (type RO/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_iecraw_lwb_s0 <= '0';
      fd_iecraw_lwb_s1 <= '0';
      fd_iecraw_lwb_s2 <= '0';
      fd_iecraw_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_iecraw_lwb_s0 <= fd_iecraw_lwb;
      fd_iecraw_lwb_s1 <= fd_iecraw_lwb_s0;
      fd_iecraw_lwb_s2 <= fd_iecraw_lwb_s1;
      if ((fd_iecraw_lwb_s1 = '1') and (fd_iecraw_lwb_s2 = '0')) then
        fd_iecraw_int <= regs_i.iecraw_i;
      end if;
    end if;
  end process;
  
  
-- Number of tagged events
-- asynchronous std_logic_vector register : Number of tagged events (type RO/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_iectag_lwb_s0 <= '0';
      fd_iectag_lwb_s1 <= '0';
      fd_iectag_lwb_s2 <= '0';
      fd_iectag_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_iectag_lwb_s0 <= fd_iectag_lwb;
      fd_iectag_lwb_s1 <= fd_iectag_lwb_s0;
      fd_iectag_lwb_s2 <= fd_iectag_lwb_s1;
      if ((fd_iectag_lwb_s1 = '1') and (fd_iectag_lwb_s2 = '0')) then
        fd_iectag_int <= regs_i.iectag_i;
      end if;
    end if;
  end process;
  
  
-- Reset stats
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.iepd_rst_stat_o <= '0';
      fd_iepd_rst_stat_sync0 <= '0';
      fd_iepd_rst_stat_sync1 <= '0';
      fd_iepd_rst_stat_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_iepd_rst_stat_sync0 <= fd_iepd_rst_stat_int;
      fd_iepd_rst_stat_sync1 <= fd_iepd_rst_stat_sync0;
      fd_iepd_rst_stat_sync2 <= fd_iepd_rst_stat_sync1;
      regs_o.iepd_rst_stat_o <= fd_iepd_rst_stat_sync2 and (not fd_iepd_rst_stat_sync1);
    end if;
  end process;
  
  
-- Processing delay
-- asynchronous std_logic_vector register : Processing delay (type RO/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_iepd_pdelay_lwb_s0 <= '0';
      fd_iepd_pdelay_lwb_s1 <= '0';
      fd_iepd_pdelay_lwb_s2 <= '0';
      fd_iepd_pdelay_int <= "00000000";
    elsif rising_edge(clk_ref_i) then
      fd_iepd_pdelay_lwb_s0 <= fd_iepd_pdelay_lwb;
      fd_iepd_pdelay_lwb_s1 <= fd_iepd_pdelay_lwb_s0;
      fd_iepd_pdelay_lwb_s2 <= fd_iepd_pdelay_lwb_s1;
      if ((fd_iepd_pdelay_lwb_s1 = '1') and (fd_iepd_pdelay_lwb_s2 = '0')) then
        fd_iepd_pdelay_int <= regs_i.iepd_pdelay_i;
      end if;
    end if;
  end process;
  
  
-- Data
  regs_o.scr_data_o <= wrdata_reg(23 downto 0);
-- Select DAC
  regs_o.scr_sel_dac_o <= fd_scr_sel_dac_int;
-- Select PLL
  regs_o.scr_sel_pll_o <= fd_scr_sel_pll_int;
-- Select GPIO
  regs_o.scr_sel_gpio_o <= fd_scr_sel_gpio_int;
-- Ready flag
-- Clock Polarity
  regs_o.scr_cpol_o <= fd_scr_cpol_int;
-- Transfer Start
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_scr_start_dly0 <= '0';
      regs_o.scr_start_o <= '0';
    elsif rising_edge(bus_clock_int) then
      fd_scr_start_dly0 <= fd_scr_start_int;
      regs_o.scr_start_o <= fd_scr_start_int and (not fd_scr_start_dly0);
    end if;
  end process;
  
  
-- Rate
-- asynchronous std_logic_vector register : Rate (type RO/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_rcrr_lwb_s0 <= '0';
      fd_rcrr_lwb_s1 <= '0';
      fd_rcrr_lwb_s2 <= '0';
      fd_rcrr_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_rcrr_lwb_s0 <= fd_rcrr_lwb;
      fd_rcrr_lwb_s1 <= fd_rcrr_lwb_s0;
      fd_rcrr_lwb_s2 <= fd_rcrr_lwb_s1;
      if ((fd_rcrr_lwb_s1 = '1') and (fd_rcrr_lwb_s2 = '0')) then
        fd_rcrr_int <= regs_i.rcrr_i;
      end if;
    end if;
  end process;
  
  
-- Frequency
-- asynchronous std_logic_vector register : Frequency (type RO/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_rcfr_lwb_s0 <= '0';
      fd_rcfr_lwb_s1 <= '0';
      fd_rcfr_lwb_s2 <= '0';
      fd_rcfr_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_rcfr_lwb_s0 <= fd_rcfr_lwb;
      fd_rcfr_lwb_s1 <= fd_rcfr_lwb_s0;
      fd_rcfr_lwb_s2 <= fd_rcfr_lwb_s1;
      if ((fd_rcfr_lwb_s1 = '1') and (fd_rcfr_lwb_s2 = '0')) then
        fd_rcfr_int <= regs_i.rcfr_i;
      end if;
    end if;
  end process;
  
  
-- Buffer enable
  regs_o.tsbcr_enable_o <= fd_tsbcr_enable_int;
-- Buffer purge
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_tsbcr_purge_dly0 <= '0';
      regs_o.tsbcr_purge_o <= '0';
    elsif rising_edge(bus_clock_int) then
      fd_tsbcr_purge_dly0 <= fd_tsbcr_purge_int;
      regs_o.tsbcr_purge_o <= fd_tsbcr_purge_int and (not fd_tsbcr_purge_dly0);
    end if;
  end process;
  
  
-- Reset TS Sequence Number
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.tsbcr_rst_seq_o <= '0';
      fd_tsbcr_rst_seq_sync0 <= '0';
      fd_tsbcr_rst_seq_sync1 <= '0';
      fd_tsbcr_rst_seq_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_tsbcr_rst_seq_sync0 <= fd_tsbcr_rst_seq_int;
      fd_tsbcr_rst_seq_sync1 <= fd_tsbcr_rst_seq_sync0;
      fd_tsbcr_rst_seq_sync2 <= fd_tsbcr_rst_seq_sync1;
      regs_o.tsbcr_rst_seq_o <= fd_tsbcr_rst_seq_sync2 and (not fd_tsbcr_rst_seq_sync1);
    end if;
  end process;
  
  
-- Buffer full
-- Buffer empty
-- UTC Value [seconds]
-- Cycles Value [in 8 ns ticks]
-- Fine Value [in phase units]
-- Timestamp Sequence ID
-- extra code for reg/fifo/mem: RAW FIFO
  fd_rawfifo_in_int(27 downto 0) <= regs_i.rawfifo_frac_i;
  fd_rawfifo_in_int(55 downto 28) <= regs_i.rawfifo_coarse_i;
  fd_rawfifo_INST : wbgen2_fifo_async
    generic map (
      g_size               => 256,
      g_width              => 56,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => regs_i.rawfifo_wr_req_i,
      wr_full_o            => regs_o.rawfifo_wr_full_o,
      rd_full_o            => open,
      rd_empty_o           => fd_rawfifo_empty_int,
      rd_usedw_o           => open,
      rd_req_i             => fd_rawfifo_rdreq_int,
      wr_clk_i             => clk_ref_i,
      rd_clk_i             => bus_clock_int,
      wr_data_i            => fd_rawfifo_in_int,
      rd_data_o            => fd_rawfifo_out_int
    );
  
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr1_enable_o <= '0';
      fd_dcr1_enable_sync0 <= '0';
      fd_dcr1_enable_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_enable_sync0 <= fd_dcr1_enable_int;
      fd_dcr1_enable_sync1 <= fd_dcr1_enable_sync0;
      regs_o.dcr1_enable_o <= fd_dcr1_enable_sync1;
    end if;
  end process;
  
  
-- Delay mode select
-- synchronizer chain for field : Delay mode select (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr1_mode_o <= '0';
      fd_dcr1_mode_sync0 <= '0';
      fd_dcr1_mode_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_mode_sync0 <= fd_dcr1_mode_int;
      fd_dcr1_mode_sync1 <= fd_dcr1_mode_sync0;
      regs_o.dcr1_mode_o <= fd_dcr1_mode_sync1;
    end if;
  end process;
  
  
-- Pulse generator arm
-- asynchronous BIT register : Pulse generator arm (type RW/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr1_pg_arm_lw_s0 <= '0';
      fd_dcr1_pg_arm_lw_s1 <= '0';
      fd_dcr1_pg_arm_lw_s2 <= '0';
      fd_dcr1_pg_arm_int_read <= '0';
      regs_o.dcr1_pg_arm_load_o <= '0';
      regs_o.dcr1_pg_arm_o <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_pg_arm_lw_s0 <= fd_dcr1_pg_arm_lw;
      fd_dcr1_pg_arm_lw_s1 <= fd_dcr1_pg_arm_lw_s0;
      fd_dcr1_pg_arm_lw_s2 <= fd_dcr1_pg_arm_lw_s1;
      if ((fd_dcr1_pg_arm_lw_s2 = '0') and (fd_dcr1_pg_arm_lw_s1 = '1')) then
        if (fd_dcr1_pg_arm_rwsel = '1') then
          regs_o.dcr1_pg_arm_o <= fd_dcr1_pg_arm_int_write;
          regs_o.dcr1_pg_arm_load_o <= '1';
        else
          regs_o.dcr1_pg_arm_load_o <= '0';
          fd_dcr1_pg_arm_int_read <= regs_i.dcr1_pg_arm_i;
        end if;
      else
        regs_o.dcr1_pg_arm_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr1_pg_trig_sync0 <= '0';
      fd_dcr1_pg_trig_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_pg_trig_sync0 <= regs_i.dcr1_pg_trig_i;
      fd_dcr1_pg_trig_sync1 <= fd_dcr1_pg_trig_sync0;
    end if;
  end process;
  
  
-- Start Delay Update
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr1_update_o <= '0';
      fd_dcr1_update_sync0 <= '0';
      fd_dcr1_update_sync1 <= '0';
      fd_dcr1_update_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_update_sync0 <= fd_dcr1_update_int;
      fd_dcr1_update_sync1 <= fd_dcr1_update_sync0;
      fd_dcr1_update_sync2 <= fd_dcr1_update_sync1;
      regs_o.dcr1_update_o <= fd_dcr1_update_sync2 and (not fd_dcr1_update_sync1);
    end if;
  end process;
  
  
-- Delay Update Done
-- synchronizer chain for field : Delay Update Done (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr1_upd_done_sync0 <= '0';
      fd_dcr1_upd_done_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_upd_done_sync0 <= regs_i.dcr1_upd_done_i;
      fd_dcr1_upd_done_sync1 <= fd_dcr1_upd_done_sync0;
    end if;
  end process;
  
  
-- Force Calibration Delay
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr1_force_dly_o <= '0';
      fd_dcr1_force_dly_sync0 <= '0';
      fd_dcr1_force_dly_sync1 <= '0';
      fd_dcr1_force_dly_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_force_dly_sync0 <= fd_dcr1_force_dly_int;
      fd_dcr1_force_dly_sync1 <= fd_dcr1_force_dly_sync0;
      fd_dcr1_force_dly_sync2 <= fd_dcr1_force_dly_sync1;
      regs_o.dcr1_force_dly_o <= fd_dcr1_force_dly_sync2 and (not fd_dcr1_force_dly_sync1);
    end if;
  end process;
  
  
-- Output Polarity
-- synchronizer chain for field : Output Polarity (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr1_pol_o <= '0';
      fd_dcr1_pol_sync0 <= '0';
      fd_dcr1_pol_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr1_pol_sync0 <= fd_dcr1_pol_int;
      fd_dcr1_pol_sync1 <= fd_dcr1_pol_sync0;
      regs_o.dcr1_pol_o <= fd_dcr1_pol_sync1;
    end if;
  end process;
  
  
-- Fine Range
-- asynchronous std_logic_vector register : Fine Range (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_frr1_swb_s0 <= '0';
      fd_frr1_swb_s1 <= '0';
      fd_frr1_swb_s2 <= '0';
      regs_o.frr1_o <= "0000000000";
    elsif rising_edge(clk_ref_i) then
      fd_frr1_swb_s0 <= fd_frr1_swb;
      fd_frr1_swb_s1 <= fd_frr1_swb_s0;
      fd_frr1_swb_s2 <= fd_frr1_swb_s1;
      if ((fd_frr1_swb_s2 = '0') and (fd_frr1_swb_s1 = '1')) then
        regs_o.frr1_o <= fd_frr1_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_start1_swb_s0 <= '0';
      fd_u_start1_swb_s1 <= '0';
      fd_u_start1_swb_s2 <= '0';
      regs_o.u_start1_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_start1_swb_s0 <= fd_u_start1_swb;
      fd_u_start1_swb_s1 <= fd_u_start1_swb_s0;
      fd_u_start1_swb_s2 <= fd_u_start1_swb_s1;
      if ((fd_u_start1_swb_s2 = '0') and (fd_u_start1_swb_s1 = '1')) then
        regs_o.u_start1_o <= fd_u_start1_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_start1_swb_s0 <= '0';
      fd_c_start1_swb_s1 <= '0';
      fd_c_start1_swb_s2 <= '0';
      regs_o.c_start1_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_start1_swb_s0 <= fd_c_start1_swb;
      fd_c_start1_swb_s1 <= fd_c_start1_swb_s0;
      fd_c_start1_swb_s2 <= fd_c_start1_swb_s1;
      if ((fd_c_start1_swb_s2 = '0') and (fd_c_start1_swb_s1 = '1')) then
        regs_o.c_start1_o <= fd_c_start1_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_start1_swb_s0 <= '0';
      fd_f_start1_swb_s1 <= '0';
      fd_f_start1_swb_s2 <= '0';
      regs_o.f_start1_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_start1_swb_s0 <= fd_f_start1_swb;
      fd_f_start1_swb_s1 <= fd_f_start1_swb_s0;
      fd_f_start1_swb_s2 <= fd_f_start1_swb_s1;
      if ((fd_f_start1_swb_s2 = '0') and (fd_f_start1_swb_s1 = '1')) then
        regs_o.f_start1_o <= fd_f_start1_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_end1_swb_s0 <= '0';
      fd_u_end1_swb_s1 <= '0';
      fd_u_end1_swb_s2 <= '0';
      regs_o.u_end1_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_end1_swb_s0 <= fd_u_end1_swb;
      fd_u_end1_swb_s1 <= fd_u_end1_swb_s0;
      fd_u_end1_swb_s2 <= fd_u_end1_swb_s1;
      if ((fd_u_end1_swb_s2 = '0') and (fd_u_end1_swb_s1 = '1')) then
        regs_o.u_end1_o <= fd_u_end1_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_end1_swb_s0 <= '0';
      fd_c_end1_swb_s1 <= '0';
      fd_c_end1_swb_s2 <= '0';
      regs_o.c_end1_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_end1_swb_s0 <= fd_c_end1_swb;
      fd_c_end1_swb_s1 <= fd_c_end1_swb_s0;
      fd_c_end1_swb_s2 <= fd_c_end1_swb_s1;
      if ((fd_c_end1_swb_s2 = '0') and (fd_c_end1_swb_s1 = '1')) then
        regs_o.c_end1_o <= fd_c_end1_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_end1_swb_s0 <= '0';
      fd_f_end1_swb_s1 <= '0';
      fd_f_end1_swb_s2 <= '0';
      regs_o.f_end1_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_end1_swb_s0 <= fd_f_end1_swb;
      fd_f_end1_swb_s1 <= fd_f_end1_swb_s0;
      fd_f_end1_swb_s2 <= fd_f_end1_swb_s1;
      if ((fd_f_end1_swb_s2 = '0') and (fd_f_end1_swb_s1 = '1')) then
        regs_o.f_end1_o <= fd_f_end1_int;
      end if;
    end if;
  end process;
  
  
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr2_enable_o <= '0';
      fd_dcr2_enable_sync0 <= '0';
      fd_dcr2_enable_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_enable_sync0 <= fd_dcr2_enable_int;
      fd_dcr2_enable_sync1 <= fd_dcr2_enable_sync0;
      regs_o.dcr2_enable_o <= fd_dcr2_enable_sync1;
    end if;
  end process;
  
  
-- Delay mode select
-- synchronizer chain for field : Delay mode select (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr2_mode_o <= '0';
      fd_dcr2_mode_sync0 <= '0';
      fd_dcr2_mode_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_mode_sync0 <= fd_dcr2_mode_int;
      fd_dcr2_mode_sync1 <= fd_dcr2_mode_sync0;
      regs_o.dcr2_mode_o <= fd_dcr2_mode_sync1;
    end if;
  end process;
  
  
-- Pulse generator arm
-- asynchronous BIT register : Pulse generator arm (type RW/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr2_pg_arm_lw_s0 <= '0';
      fd_dcr2_pg_arm_lw_s1 <= '0';
      fd_dcr2_pg_arm_lw_s2 <= '0';
      fd_dcr2_pg_arm_int_read <= '0';
      regs_o.dcr2_pg_arm_load_o <= '0';
      regs_o.dcr2_pg_arm_o <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_pg_arm_lw_s0 <= fd_dcr2_pg_arm_lw;
      fd_dcr2_pg_arm_lw_s1 <= fd_dcr2_pg_arm_lw_s0;
      fd_dcr2_pg_arm_lw_s2 <= fd_dcr2_pg_arm_lw_s1;
      if ((fd_dcr2_pg_arm_lw_s2 = '0') and (fd_dcr2_pg_arm_lw_s1 = '1')) then
        if (fd_dcr2_pg_arm_rwsel = '1') then
          regs_o.dcr2_pg_arm_o <= fd_dcr2_pg_arm_int_write;
          regs_o.dcr2_pg_arm_load_o <= '1';
        else
          regs_o.dcr2_pg_arm_load_o <= '0';
          fd_dcr2_pg_arm_int_read <= regs_i.dcr2_pg_arm_i;
        end if;
      else
        regs_o.dcr2_pg_arm_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr2_pg_trig_sync0 <= '0';
      fd_dcr2_pg_trig_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_pg_trig_sync0 <= regs_i.dcr2_pg_trig_i;
      fd_dcr2_pg_trig_sync1 <= fd_dcr2_pg_trig_sync0;
    end if;
  end process;
  
  
-- Start Delay Update
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr2_update_o <= '0';
      fd_dcr2_update_sync0 <= '0';
      fd_dcr2_update_sync1 <= '0';
      fd_dcr2_update_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_update_sync0 <= fd_dcr2_update_int;
      fd_dcr2_update_sync1 <= fd_dcr2_update_sync0;
      fd_dcr2_update_sync2 <= fd_dcr2_update_sync1;
      regs_o.dcr2_update_o <= fd_dcr2_update_sync2 and (not fd_dcr2_update_sync1);
    end if;
  end process;
  
  
-- Delay Update Done
-- synchronizer chain for field : Delay Update Done (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr2_upd_done_sync0 <= '0';
      fd_dcr2_upd_done_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_upd_done_sync0 <= regs_i.dcr2_upd_done_i;
      fd_dcr2_upd_done_sync1 <= fd_dcr2_upd_done_sync0;
    end if;
  end process;
  
  
-- Force Calibration Delay
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr2_force_dly_o <= '0';
      fd_dcr2_force_dly_sync0 <= '0';
      fd_dcr2_force_dly_sync1 <= '0';
      fd_dcr2_force_dly_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_force_dly_sync0 <= fd_dcr2_force_dly_int;
      fd_dcr2_force_dly_sync1 <= fd_dcr2_force_dly_sync0;
      fd_dcr2_force_dly_sync2 <= fd_dcr2_force_dly_sync1;
      regs_o.dcr2_force_dly_o <= fd_dcr2_force_dly_sync2 and (not fd_dcr2_force_dly_sync1);
    end if;
  end process;
  
  
-- Output Polarity
-- synchronizer chain for field : Output Polarity (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr2_pol_o <= '0';
      fd_dcr2_pol_sync0 <= '0';
      fd_dcr2_pol_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr2_pol_sync0 <= fd_dcr2_pol_int;
      fd_dcr2_pol_sync1 <= fd_dcr2_pol_sync0;
      regs_o.dcr2_pol_o <= fd_dcr2_pol_sync1;
    end if;
  end process;
  
  
-- Fine Range
-- asynchronous std_logic_vector register : Fine Range (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_frr2_swb_s0 <= '0';
      fd_frr2_swb_s1 <= '0';
      fd_frr2_swb_s2 <= '0';
      regs_o.frr2_o <= "0000000000";
    elsif rising_edge(clk_ref_i) then
      fd_frr2_swb_s0 <= fd_frr2_swb;
      fd_frr2_swb_s1 <= fd_frr2_swb_s0;
      fd_frr2_swb_s2 <= fd_frr2_swb_s1;
      if ((fd_frr2_swb_s2 = '0') and (fd_frr2_swb_s1 = '1')) then
        regs_o.frr2_o <= fd_frr2_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_start2_swb_s0 <= '0';
      fd_u_start2_swb_s1 <= '0';
      fd_u_start2_swb_s2 <= '0';
      regs_o.u_start2_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_start2_swb_s0 <= fd_u_start2_swb;
      fd_u_start2_swb_s1 <= fd_u_start2_swb_s0;
      fd_u_start2_swb_s2 <= fd_u_start2_swb_s1;
      if ((fd_u_start2_swb_s2 = '0') and (fd_u_start2_swb_s1 = '1')) then
        regs_o.u_start2_o <= fd_u_start2_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_start2_swb_s0 <= '0';
      fd_c_start2_swb_s1 <= '0';
      fd_c_start2_swb_s2 <= '0';
      regs_o.c_start2_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_start2_swb_s0 <= fd_c_start2_swb;
      fd_c_start2_swb_s1 <= fd_c_start2_swb_s0;
      fd_c_start2_swb_s2 <= fd_c_start2_swb_s1;
      if ((fd_c_start2_swb_s2 = '0') and (fd_c_start2_swb_s1 = '1')) then
        regs_o.c_start2_o <= fd_c_start2_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_start2_swb_s0 <= '0';
      fd_f_start2_swb_s1 <= '0';
      fd_f_start2_swb_s2 <= '0';
      regs_o.f_start2_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_start2_swb_s0 <= fd_f_start2_swb;
      fd_f_start2_swb_s1 <= fd_f_start2_swb_s0;
      fd_f_start2_swb_s2 <= fd_f_start2_swb_s1;
      if ((fd_f_start2_swb_s2 = '0') and (fd_f_start2_swb_s1 = '1')) then
        regs_o.f_start2_o <= fd_f_start2_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_end2_swb_s0 <= '0';
      fd_u_end2_swb_s1 <= '0';
      fd_u_end2_swb_s2 <= '0';
      regs_o.u_end2_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_end2_swb_s0 <= fd_u_end2_swb;
      fd_u_end2_swb_s1 <= fd_u_end2_swb_s0;
      fd_u_end2_swb_s2 <= fd_u_end2_swb_s1;
      if ((fd_u_end2_swb_s2 = '0') and (fd_u_end2_swb_s1 = '1')) then
        regs_o.u_end2_o <= fd_u_end2_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_end2_swb_s0 <= '0';
      fd_c_end2_swb_s1 <= '0';
      fd_c_end2_swb_s2 <= '0';
      regs_o.c_end2_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_end2_swb_s0 <= fd_c_end2_swb;
      fd_c_end2_swb_s1 <= fd_c_end2_swb_s0;
      fd_c_end2_swb_s2 <= fd_c_end2_swb_s1;
      if ((fd_c_end2_swb_s2 = '0') and (fd_c_end2_swb_s1 = '1')) then
        regs_o.c_end2_o <= fd_c_end2_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_end2_swb_s0 <= '0';
      fd_f_end2_swb_s1 <= '0';
      fd_f_end2_swb_s2 <= '0';
      regs_o.f_end2_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_end2_swb_s0 <= fd_f_end2_swb;
      fd_f_end2_swb_s1 <= fd_f_end2_swb_s0;
      fd_f_end2_swb_s2 <= fd_f_end2_swb_s1;
      if ((fd_f_end2_swb_s2 = '0') and (fd_f_end2_swb_s1 = '1')) then
        regs_o.f_end2_o <= fd_f_end2_int;
      end if;
    end if;
  end process;
  
  
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr3_enable_o <= '0';
      fd_dcr3_enable_sync0 <= '0';
      fd_dcr3_enable_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_enable_sync0 <= fd_dcr3_enable_int;
      fd_dcr3_enable_sync1 <= fd_dcr3_enable_sync0;
      regs_o.dcr3_enable_o <= fd_dcr3_enable_sync1;
    end if;
  end process;
  
  
-- Delay mode select
-- synchronizer chain for field : Delay mode select (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr3_mode_o <= '0';
      fd_dcr3_mode_sync0 <= '0';
      fd_dcr3_mode_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_mode_sync0 <= fd_dcr3_mode_int;
      fd_dcr3_mode_sync1 <= fd_dcr3_mode_sync0;
      regs_o.dcr3_mode_o <= fd_dcr3_mode_sync1;
    end if;
  end process;
  
  
-- Pulse generator arm
-- asynchronous BIT register : Pulse generator arm (type RW/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr3_pg_arm_lw_s0 <= '0';
      fd_dcr3_pg_arm_lw_s1 <= '0';
      fd_dcr3_pg_arm_lw_s2 <= '0';
      fd_dcr3_pg_arm_int_read <= '0';
      regs_o.dcr3_pg_arm_load_o <= '0';
      regs_o.dcr3_pg_arm_o <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_pg_arm_lw_s0 <= fd_dcr3_pg_arm_lw;
      fd_dcr3_pg_arm_lw_s1 <= fd_dcr3_pg_arm_lw_s0;
      fd_dcr3_pg_arm_lw_s2 <= fd_dcr3_pg_arm_lw_s1;
      if ((fd_dcr3_pg_arm_lw_s2 = '0') and (fd_dcr3_pg_arm_lw_s1 = '1')) then
        if (fd_dcr3_pg_arm_rwsel = '1') then
          regs_o.dcr3_pg_arm_o <= fd_dcr3_pg_arm_int_write;
          regs_o.dcr3_pg_arm_load_o <= '1';
        else
          regs_o.dcr3_pg_arm_load_o <= '0';
          fd_dcr3_pg_arm_int_read <= regs_i.dcr3_pg_arm_i;
        end if;
      else
        regs_o.dcr3_pg_arm_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr3_pg_trig_sync0 <= '0';
      fd_dcr3_pg_trig_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_pg_trig_sync0 <= regs_i.dcr3_pg_trig_i;
      fd_dcr3_pg_trig_sync1 <= fd_dcr3_pg_trig_sync0;
    end if;
  end process;
  
  
-- Start Delay Update
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr3_update_o <= '0';
      fd_dcr3_update_sync0 <= '0';
      fd_dcr3_update_sync1 <= '0';
      fd_dcr3_update_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_update_sync0 <= fd_dcr3_update_int;
      fd_dcr3_update_sync1 <= fd_dcr3_update_sync0;
      fd_dcr3_update_sync2 <= fd_dcr3_update_sync1;
      regs_o.dcr3_update_o <= fd_dcr3_update_sync2 and (not fd_dcr3_update_sync1);
    end if;
  end process;
  
  
-- Delay Update Done
-- synchronizer chain for field : Delay Update Done (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr3_upd_done_sync0 <= '0';
      fd_dcr3_upd_done_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_upd_done_sync0 <= regs_i.dcr3_upd_done_i;
      fd_dcr3_upd_done_sync1 <= fd_dcr3_upd_done_sync0;
    end if;
  end process;
  
  
-- Force Calibration Delay
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr3_force_dly_o <= '0';
      fd_dcr3_force_dly_sync0 <= '0';
      fd_dcr3_force_dly_sync1 <= '0';
      fd_dcr3_force_dly_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_force_dly_sync0 <= fd_dcr3_force_dly_int;
      fd_dcr3_force_dly_sync1 <= fd_dcr3_force_dly_sync0;
      fd_dcr3_force_dly_sync2 <= fd_dcr3_force_dly_sync1;
      regs_o.dcr3_force_dly_o <= fd_dcr3_force_dly_sync2 and (not fd_dcr3_force_dly_sync1);
    end if;
  end process;
  
  
-- Output Polarity
-- synchronizer chain for field : Output Polarity (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr3_pol_o <= '0';
      fd_dcr3_pol_sync0 <= '0';
      fd_dcr3_pol_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr3_pol_sync0 <= fd_dcr3_pol_int;
      fd_dcr3_pol_sync1 <= fd_dcr3_pol_sync0;
      regs_o.dcr3_pol_o <= fd_dcr3_pol_sync1;
    end if;
  end process;
  
  
-- Fine Range
-- asynchronous std_logic_vector register : Fine Range (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_frr3_swb_s0 <= '0';
      fd_frr3_swb_s1 <= '0';
      fd_frr3_swb_s2 <= '0';
      regs_o.frr3_o <= "0000000000";
    elsif rising_edge(clk_ref_i) then
      fd_frr3_swb_s0 <= fd_frr3_swb;
      fd_frr3_swb_s1 <= fd_frr3_swb_s0;
      fd_frr3_swb_s2 <= fd_frr3_swb_s1;
      if ((fd_frr3_swb_s2 = '0') and (fd_frr3_swb_s1 = '1')) then
        regs_o.frr3_o <= fd_frr3_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_start3_swb_s0 <= '0';
      fd_u_start3_swb_s1 <= '0';
      fd_u_start3_swb_s2 <= '0';
      regs_o.u_start3_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_start3_swb_s0 <= fd_u_start3_swb;
      fd_u_start3_swb_s1 <= fd_u_start3_swb_s0;
      fd_u_start3_swb_s2 <= fd_u_start3_swb_s1;
      if ((fd_u_start3_swb_s2 = '0') and (fd_u_start3_swb_s1 = '1')) then
        regs_o.u_start3_o <= fd_u_start3_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_start3_swb_s0 <= '0';
      fd_c_start3_swb_s1 <= '0';
      fd_c_start3_swb_s2 <= '0';
      regs_o.c_start3_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_start3_swb_s0 <= fd_c_start3_swb;
      fd_c_start3_swb_s1 <= fd_c_start3_swb_s0;
      fd_c_start3_swb_s2 <= fd_c_start3_swb_s1;
      if ((fd_c_start3_swb_s2 = '0') and (fd_c_start3_swb_s1 = '1')) then
        regs_o.c_start3_o <= fd_c_start3_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_start3_swb_s0 <= '0';
      fd_f_start3_swb_s1 <= '0';
      fd_f_start3_swb_s2 <= '0';
      regs_o.f_start3_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_start3_swb_s0 <= fd_f_start3_swb;
      fd_f_start3_swb_s1 <= fd_f_start3_swb_s0;
      fd_f_start3_swb_s2 <= fd_f_start3_swb_s1;
      if ((fd_f_start3_swb_s2 = '0') and (fd_f_start3_swb_s1 = '1')) then
        regs_o.f_start3_o <= fd_f_start3_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_end3_swb_s0 <= '0';
      fd_u_end3_swb_s1 <= '0';
      fd_u_end3_swb_s2 <= '0';
      regs_o.u_end3_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_end3_swb_s0 <= fd_u_end3_swb;
      fd_u_end3_swb_s1 <= fd_u_end3_swb_s0;
      fd_u_end3_swb_s2 <= fd_u_end3_swb_s1;
      if ((fd_u_end3_swb_s2 = '0') and (fd_u_end3_swb_s1 = '1')) then
        regs_o.u_end3_o <= fd_u_end3_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_end3_swb_s0 <= '0';
      fd_c_end3_swb_s1 <= '0';
      fd_c_end3_swb_s2 <= '0';
      regs_o.c_end3_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_end3_swb_s0 <= fd_c_end3_swb;
      fd_c_end3_swb_s1 <= fd_c_end3_swb_s0;
      fd_c_end3_swb_s2 <= fd_c_end3_swb_s1;
      if ((fd_c_end3_swb_s2 = '0') and (fd_c_end3_swb_s1 = '1')) then
        regs_o.c_end3_o <= fd_c_end3_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_end3_swb_s0 <= '0';
      fd_f_end3_swb_s1 <= '0';
      fd_f_end3_swb_s2 <= '0';
      regs_o.f_end3_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_end3_swb_s0 <= fd_f_end3_swb;
      fd_f_end3_swb_s1 <= fd_f_end3_swb_s0;
      fd_f_end3_swb_s2 <= fd_f_end3_swb_s1;
      if ((fd_f_end3_swb_s2 = '0') and (fd_f_end3_swb_s1 = '1')) then
        regs_o.f_end3_o <= fd_f_end3_int;
      end if;
    end if;
  end process;
  
  
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr4_enable_o <= '0';
      fd_dcr4_enable_sync0 <= '0';
      fd_dcr4_enable_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_enable_sync0 <= fd_dcr4_enable_int;
      fd_dcr4_enable_sync1 <= fd_dcr4_enable_sync0;
      regs_o.dcr4_enable_o <= fd_dcr4_enable_sync1;
    end if;
  end process;
  
  
-- Delay mode select
-- synchronizer chain for field : Delay mode select (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr4_mode_o <= '0';
      fd_dcr4_mode_sync0 <= '0';
      fd_dcr4_mode_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_mode_sync0 <= fd_dcr4_mode_int;
      fd_dcr4_mode_sync1 <= fd_dcr4_mode_sync0;
      regs_o.dcr4_mode_o <= fd_dcr4_mode_sync1;
    end if;
  end process;
  
  
-- Pulse generator arm
-- asynchronous BIT register : Pulse generator arm (type RW/WO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr4_pg_arm_lw_s0 <= '0';
      fd_dcr4_pg_arm_lw_s1 <= '0';
      fd_dcr4_pg_arm_lw_s2 <= '0';
      fd_dcr4_pg_arm_int_read <= '0';
      regs_o.dcr4_pg_arm_load_o <= '0';
      regs_o.dcr4_pg_arm_o <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_pg_arm_lw_s0 <= fd_dcr4_pg_arm_lw;
      fd_dcr4_pg_arm_lw_s1 <= fd_dcr4_pg_arm_lw_s0;
      fd_dcr4_pg_arm_lw_s2 <= fd_dcr4_pg_arm_lw_s1;
      if ((fd_dcr4_pg_arm_lw_s2 = '0') and (fd_dcr4_pg_arm_lw_s1 = '1')) then
        if (fd_dcr4_pg_arm_rwsel = '1') then
          regs_o.dcr4_pg_arm_o <= fd_dcr4_pg_arm_int_write;
          regs_o.dcr4_pg_arm_load_o <= '1';
        else
          regs_o.dcr4_pg_arm_load_o <= '0';
          fd_dcr4_pg_arm_int_read <= regs_i.dcr4_pg_arm_i;
        end if;
      else
        regs_o.dcr4_pg_arm_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr4_pg_trig_sync0 <= '0';
      fd_dcr4_pg_trig_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_pg_trig_sync0 <= regs_i.dcr4_pg_trig_i;
      fd_dcr4_pg_trig_sync1 <= fd_dcr4_pg_trig_sync0;
    end if;
  end process;
  
  
-- Start Delay Update
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr4_update_o <= '0';
      fd_dcr4_update_sync0 <= '0';
      fd_dcr4_update_sync1 <= '0';
      fd_dcr4_update_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_update_sync0 <= fd_dcr4_update_int;
      fd_dcr4_update_sync1 <= fd_dcr4_update_sync0;
      fd_dcr4_update_sync2 <= fd_dcr4_update_sync1;
      regs_o.dcr4_update_o <= fd_dcr4_update_sync2 and (not fd_dcr4_update_sync1);
    end if;
  end process;
  
  
-- Delay Update Done
-- synchronizer chain for field : Delay Update Done (type RO/WO, clk_ref_i -> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_dcr4_upd_done_sync0 <= '0';
      fd_dcr4_upd_done_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_upd_done_sync0 <= regs_i.dcr4_upd_done_i;
      fd_dcr4_upd_done_sync1 <= fd_dcr4_upd_done_sync0;
    end if;
  end process;
  
  
-- Force Calibration Delay
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr4_force_dly_o <= '0';
      fd_dcr4_force_dly_sync0 <= '0';
      fd_dcr4_force_dly_sync1 <= '0';
      fd_dcr4_force_dly_sync2 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_force_dly_sync0 <= fd_dcr4_force_dly_int;
      fd_dcr4_force_dly_sync1 <= fd_dcr4_force_dly_sync0;
      fd_dcr4_force_dly_sync2 <= fd_dcr4_force_dly_sync1;
      regs_o.dcr4_force_dly_o <= fd_dcr4_force_dly_sync2 and (not fd_dcr4_force_dly_sync1);
    end if;
  end process;
  
  
-- Output Polarity
-- synchronizer chain for field : Output Polarity (type RW/RO, bus_clock_int <-> clk_ref_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.dcr4_pol_o <= '0';
      fd_dcr4_pol_sync0 <= '0';
      fd_dcr4_pol_sync1 <= '0';
    elsif rising_edge(clk_ref_i) then
      fd_dcr4_pol_sync0 <= fd_dcr4_pol_int;
      fd_dcr4_pol_sync1 <= fd_dcr4_pol_sync0;
      regs_o.dcr4_pol_o <= fd_dcr4_pol_sync1;
    end if;
  end process;
  
  
-- Fine Range
-- asynchronous std_logic_vector register : Fine Range (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_frr4_swb_s0 <= '0';
      fd_frr4_swb_s1 <= '0';
      fd_frr4_swb_s2 <= '0';
      regs_o.frr4_o <= "0000000000";
    elsif rising_edge(clk_ref_i) then
      fd_frr4_swb_s0 <= fd_frr4_swb;
      fd_frr4_swb_s1 <= fd_frr4_swb_s0;
      fd_frr4_swb_s2 <= fd_frr4_swb_s1;
      if ((fd_frr4_swb_s2 = '0') and (fd_frr4_swb_s1 = '1')) then
        regs_o.frr4_o <= fd_frr4_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_start4_swb_s0 <= '0';
      fd_u_start4_swb_s1 <= '0';
      fd_u_start4_swb_s2 <= '0';
      regs_o.u_start4_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_start4_swb_s0 <= fd_u_start4_swb;
      fd_u_start4_swb_s1 <= fd_u_start4_swb_s0;
      fd_u_start4_swb_s2 <= fd_u_start4_swb_s1;
      if ((fd_u_start4_swb_s2 = '0') and (fd_u_start4_swb_s1 = '1')) then
        regs_o.u_start4_o <= fd_u_start4_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_start4_swb_s0 <= '0';
      fd_c_start4_swb_s1 <= '0';
      fd_c_start4_swb_s2 <= '0';
      regs_o.c_start4_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_start4_swb_s0 <= fd_c_start4_swb;
      fd_c_start4_swb_s1 <= fd_c_start4_swb_s0;
      fd_c_start4_swb_s2 <= fd_c_start4_swb_s1;
      if ((fd_c_start4_swb_s2 = '0') and (fd_c_start4_swb_s1 = '1')) then
        regs_o.c_start4_o <= fd_c_start4_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_start4_swb_s0 <= '0';
      fd_f_start4_swb_s1 <= '0';
      fd_f_start4_swb_s2 <= '0';
      regs_o.f_start4_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_start4_swb_s0 <= fd_f_start4_swb;
      fd_f_start4_swb_s1 <= fd_f_start4_swb_s0;
      fd_f_start4_swb_s2 <= fd_f_start4_swb_s1;
      if ((fd_f_start4_swb_s2 = '0') and (fd_f_start4_swb_s1 = '1')) then
        regs_o.f_start4_o <= fd_f_start4_int;
      end if;
    end if;
  end process;
  
  
-- UTC seconds
-- asynchronous std_logic_vector register : UTC seconds (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_u_end4_swb_s0 <= '0';
      fd_u_end4_swb_s1 <= '0';
      fd_u_end4_swb_s2 <= '0';
      regs_o.u_end4_o <= "00000000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_u_end4_swb_s0 <= fd_u_end4_swb;
      fd_u_end4_swb_s1 <= fd_u_end4_swb_s0;
      fd_u_end4_swb_s2 <= fd_u_end4_swb_s1;
      if ((fd_u_end4_swb_s2 = '0') and (fd_u_end4_swb_s1 = '1')) then
        regs_o.u_end4_o <= fd_u_end4_int;
      end if;
    end if;
  end process;
  
  
-- Refclk cycles
-- asynchronous std_logic_vector register : Refclk cycles (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_c_end4_swb_s0 <= '0';
      fd_c_end4_swb_s1 <= '0';
      fd_c_end4_swb_s2 <= '0';
      regs_o.c_end4_o <= "0000000000000000000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_c_end4_swb_s0 <= fd_c_end4_swb;
      fd_c_end4_swb_s1 <= fd_c_end4_swb_s0;
      fd_c_end4_swb_s2 <= fd_c_end4_swb_s1;
      if ((fd_c_end4_swb_s2 = '0') and (fd_c_end4_swb_s1 = '1')) then
        regs_o.c_end4_o <= fd_c_end4_int;
      end if;
    end if;
  end process;
  
  
-- Fractional part
-- asynchronous std_logic_vector register : Fractional part (type RW/RO, clk_ref_i <-> bus_clock_int)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_f_end4_swb_s0 <= '0';
      fd_f_end4_swb_s1 <= '0';
      fd_f_end4_swb_s2 <= '0';
      regs_o.f_end4_o <= "000000000000";
    elsif rising_edge(clk_ref_i) then
      fd_f_end4_swb_s0 <= fd_f_end4_swb;
      fd_f_end4_swb_s1 <= fd_f_end4_swb_s0;
      fd_f_end4_swb_s2 <= fd_f_end4_swb_s1;
      if ((fd_f_end4_swb_s2 = '0') and (fd_f_end4_swb_s1 = '1')) then
        regs_o.f_end4_o <= fd_f_end4_int;
      end if;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
  eic_ier_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt status register
  eic_isr_clear_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
      g_num_interrupts     => 1,
      g_irq00_mode         => 2,
      g_irq01_mode         => 0,
      g_irq02_mode         => 0,
      g_irq03_mode         => 0,
      g_irq04_mode         => 0,
      g_irq05_mode         => 0,
      g_irq06_mode         => 0,
      g_irq07_mode         => 0,
      g_irq08_mode         => 0,
      g_irq09_mode         => 0,
      g_irq0a_mode         => 0,
      g_irq0b_mode         => 0,
      g_irq0c_mode         => 0,
      g_irq0d_mode         => 0,
      g_irq0e_mode         => 0,
      g_irq0f_mode         => 0,
      g_irq10_mode         => 0,
      g_irq11_mode         => 0,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => bus_clock_int,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_irq_o
    );
  
  irq_inputs_vector_int(0) <= irq_ts_buf_notempty_i;
-- extra code for reg/fifo/mem: FIFO 'RAW FIFO' data output register 0
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fd_rawfifo_rdreq_int_d0 <= '0';
    elsif rising_edge(bus_clock_int) then
      fd_rawfifo_rdreq_int_d0 <= fd_rawfifo_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'RAW FIFO' data output register 1
  rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
