-- file: clk_wiz_v3_2.vhd
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------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___125.000______0.000______50.0______161.194____212.907
-- CLK_OUT2___125.000____180.000______50.0______161.194____212.907
--
------------------------------------------------------------------------------
-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________125.000____________0.010

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity fd_ddr_pll is
  port
    (
      RST : in std_logic;
      LOCKED : out std_logic;
      -- Clock in ports
      CLK_IN1_P : in  std_logic;
      CLK_IN1_N : in  std_logic;
      -- Clock out ports
      CLK_OUT1  : out std_logic;
      CLK_OUT2  : out std_logic
      );
end fd_ddr_pll;

architecture xilinx of fd_ddr_pll is
  attribute CORE_GENERATION_INFO           : string;
  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_2,clk_wiz_v3_2,{component_name=clk_wiz_v3_2,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=8.000,clkin2_period=8.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
  -- Input clock buffering / unused connectors
  signal clkin1                            : std_logic;
  -- Output clock buffering / unused connectors
  signal clkfbout                          : std_logic;
  signal clkfbout_buf                      : std_logic;
  signal clkout0                           : std_logic;
  signal clkout1                           : std_logic;
  signal clkout2_unused                    : std_logic;
  signal clkout3_unused                    : std_logic;
  signal clkout4_unused                    : std_logic;
  signal clkout5_unused                    : std_logic;
  -- Unused status signals
  signal locked_unused                     : std_logic;

begin


  -- Input buffering
  --------------------------------------
  clkin1_buf : IBUFGDS
    generic map
    (
      DIFF_TERM    => true,             -- Differential Termination
      IBUF_LOW_PWR => false,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD   => "LVDS_25")
    port map
    (O  => clkin1,
     I  => CLK_IN1_P,
     IB => CLK_IN1_N);


  -- Clocking primitive
  --------------------------------------
  -- Instantiation of the PLL primitive
  --    * Unused inputs are tied off
  --    * Unused outputs are labeled unused

  pll_base_inst : PLL_BASE
    generic map
    (BANDWIDTH          => "OPTIMIZED",
     CLK_FEEDBACK       => "CLKFBOUT",
     COMPENSATION       => "SYSTEM_SYNCHRONOUS",
     DIVCLK_DIVIDE      => 1,
     CLKFBOUT_MULT      => 4,
     CLKFBOUT_PHASE     => 0.000,
     CLKOUT0_DIVIDE     => 4,
     CLKOUT0_PHASE      => 0.000,
     CLKOUT0_DUTY_CYCLE => 0.500,
     CLKOUT1_DIVIDE     => 4,
     CLKOUT1_PHASE      => 180.000,
     CLKOUT1_DUTY_CYCLE => 0.500,
     CLKIN_PERIOD       => 8.000,
     REF_JITTER         => 0.010)
    port map
    -- Output clocks
    (CLKFBOUT => clkfbout,
     CLKOUT0  => clkout0,
     CLKOUT1  => clkout1,
     CLKOUT2  => clkout2_unused,
     CLKOUT3  => clkout3_unused,
     CLKOUT4  => clkout4_unused,
     CLKOUT5  => clkout5_unused,
     LOCKED   => LOCKED,
     RST      => RST,
     -- Input clock control
     CLKFBIN  => clkfbout_buf,
     CLKIN    => clkin1);

  -- Output buffering
  -------------------------------------
  clkf_buf : BUFG
    port map
    (O => clkfbout_buf,
     I => clkfbout);


  clkout1_buf : BUFG
    port map
    (O => CLK_OUT1,
     I => clkout0);



  clkout2_buf : BUFG
    port map
    (O => CLK_OUT2,
     I => clkout1);

end xilinx;
