Commit 1b63405e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

testbench/vme_irq: check behaviour of multiple SVECs on same bus

parent 8ea34c3d
......@@ -36,8 +36,8 @@ module svec_vme_buffers (
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
// output VME_IACKIN_n_o,
// input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
......@@ -66,8 +66,8 @@ module svec_vme_buffers (
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
pullup(slave.iackout_n);
// pullup(slave.iackin_n);
// pullup(slave.iackout_n);
genvar i;
......@@ -87,7 +87,7 @@ module svec_vme_buffers (
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
// assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
......@@ -100,60 +100,62 @@ module svec_vme_buffers (
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.dtack_n = VME_DTACK_OE_i ? VME_DTACK_n_i : 1'bz;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
assign slave.iackout_n = VME_IACKOUT_n_i;
// assign slave.iackout_n = VME_IACKOUT_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(VME_BBSY_n),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
`define DECLARE_VME_BUFFERS(iface,slot) \
wire VME_AS_n_``slot;\
wire VME_RST_n_``slot;\
wire VME_WRITE_n_``slot;\
wire [5:0] VME_AM_``slot;\
wire [1:0] VME_DS_n_``slot;\
wire VME_BERR_``slot;\
wire VME_DTACK_n_``slot;\
wire VME_RETRY_n_``slot;\
wire VME_RETRY_OE_``slot;\
wire VME_LWORD_n_``slot;\
wire [31:1]VME_ADDR_``slot;\
wire [31:0]VME_DATA_``slot;\
wire VME_BBSY_n_``slot;\
wire [6:0]VME_IRQ_n_``slot;\
wire VME_IACK_n_``slot;\
// wire VME_IACKOUT_n_``slot;\
wire VME_DTACK_OE_``slot;\
wire VME_DATA_DIR_``slot;\
wire VME_DATA_OE_N_``slot;\
wire VME_ADDR_DIR_``slot;\
wire VME_ADDR_OE_N_``slot;\
svec_vme_buffers U_VME_Bufs_``slot ( \
.VME_AS_n_o(VME_AS_n_``slot),\
.VME_RST_n_o(VME_RST_n_``slot),\
.VME_WRITE_n_o(VME_WRITE_n_``slot),\
.VME_AM_o(VME_AM_``slot),\
.VME_DS_n_o(VME_DS_n_``slot),\
.VME_BERR_i(VME_BERR_``slot),\
.VME_DTACK_n_i(VME_DTACK_n_``slot),\
.VME_RETRY_n_i(VME_RETRY_n_``slot),\
.VME_RETRY_OE_i(VME_RETRY_OE_``slot),\
.VME_LWORD_n_b(VME_LWORD_n_``slot),\
.VME_ADDR_b(VME_ADDR_``slot),\
.VME_DATA_b(VME_DATA_``slot),\
.VME_BBSY_n_o(VME_BBSY_n_``slot),\
.VME_IRQ_n_i(VME_IRQ_n_``slot),\
.VME_IACK_n_o(VME_IACK_n_``slot),\
// .VME_IACKIN_n_o(VME_IACKIN_n_``slot),\
// .VME_IACKOUT_n_i(VME_IACKOUT_n_``slot),\
.VME_DTACK_OE_i(VME_DTACK_OE_``slot),\
.VME_DATA_DIR_i(VME_DATA_DIR_``slot),\
.VME_DATA_OE_N_i(VME_DATA_OE_N_``slot),\
.VME_ADDR_DIR_i(VME_ADDR_DIR_``slot),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N_``slot),\
.slave(iface)\
);
......@@ -164,30 +166,30 @@ endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_IRQ_n_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
`define WIRE_VME_PINS(slot) \
.VME_AS_n_i(VME_AS_n_``slot),\
.VME_RST_n_i(VME_RST_n_``slot),\
.VME_WRITE_n_i(VME_WRITE_n_``slot),\
.VME_AM_i(VME_AM_``slot),\
.VME_DS_n_i(VME_DS_n_``slot),\
.VME_GA_i(_gen_ga(slot)),\
.VME_BERR_o(VME_BERR_``slot),\
.VME_DTACK_n_o(VME_DTACK_n_``slot),\
.VME_RETRY_n_o(VME_RETRY_n_``slot),\
.VME_RETRY_OE_o(VME_RETRY_OE_``slot),\
.VME_LWORD_n_b(VME_LWORD_n_``slot),\
.VME_ADDR_b(VME_ADDR_``slot),\
.VME_DATA_b(VME_DATA_``slot),\
.VME_BBSY_n_i(VME_BBSY_n_``slot),\
.VME_IRQ_n_o(VME_IRQ_n_``slot),\
.VME_IACK_n_i(VME_IACK_n_``slot),\
// .VME_IACKIN_n_i(VME_IACKIN_n_``slot),\
// .VME_IACKOUT_n_o(VME_IACKOUT_n_``slot),\
.VME_DTACK_OE_o(VME_DTACK_OE_``slot),\
.VME_DATA_DIR_o(VME_DATA_DIR_``slot),\
.VME_DATA_OE_N_o(VME_DATA_OE_N_``slot),\
.VME_ADDR_DIR_o(VME_ADDR_DIR_``slot),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N_``slot)
\ No newline at end of file
......@@ -37,7 +37,7 @@ interface IVME64X ( input sys_rst_n_i );
wire [31:0] data;
wire bbsy_n;
wire [6:0] irq_n;
wire iackin_n, iackout_n, iack_n;
wire iack_n;
logic q_as_n = 1'bz;
logic q_rst_n = 1'bz;
......@@ -52,7 +52,7 @@ interface IVME64X ( input sys_rst_n_i );
logic [31:0] q_data = 32'bz;
logic q_bbsy_n = 1'bz;
logic [6:0] q_irq_n = 7'bz;
logic q_iackin_n = 1'bz, q_iackout_n = 1'bz, q_iack_n = 1'bz;
logic q_iack_n = 1'bz;
/* SystemVerilog does not allow pullups inside interfaces or on logic type */
......@@ -71,8 +71,6 @@ interface IVME64X ( input sys_rst_n_i );
assign data = q_data;
assign bbsy_n = q_bbsy_n;
assign irq_n = q_irq_n;
assign iackin_n = q_iackin_n;
assign iackout_n = q_iackout_n;
assign iack_n = q_iack_n;
// VME Master
......@@ -85,11 +83,9 @@ interface IVME64X ( input sys_rst_n_i );
output ds_n,
output ga,
output bbsy_n,
output iackin_n,
output iack_n,
input berr_n,
input irq_n,
input iackout_n,
inout addr,
inout data,
inout lword_n,
......@@ -103,11 +99,9 @@ interface IVME64X ( input sys_rst_n_i );
input q_ds_n,
input q_ga,
input q_bbsy_n,
input q_iackin_n,
input q_iack_n,
input q_berr_n,
input q_irq_n,
input q_iackout_n,
input q_addr,
input q_data,
input q_lword_n,
......@@ -124,11 +118,9 @@ interface IVME64X ( input sys_rst_n_i );
output ds_n,
output ga,
output bbsy_n,
output iackin_n,
output iack_n,
input berr_n,
input irq_n,
input iackout_n,
inout addr,
inout data,
inout lword_n,
......@@ -146,11 +138,9 @@ interface IVME64X ( input sys_rst_n_i );
input ds_n,
input ga,
input bbsy_n,
input iackin_n,
input iack_n,
output berr_n,
output irq_n,
output iackout_n,
inout addr,
inout data,
inout lword_n,
......@@ -211,10 +201,21 @@ class CBusAccessor_VME64x extends CBusAccessor;
function new(virtual IVME64X.tb _vme);
vme = _vme;
m_ga = 6'b010111;
vme.q_ga = m_ga;
m_ga = 06'b010111;
// vme.q_ga = m_ga;
endfunction // new
task set_slot(int slot);
m_ga = ~slot;
m_ga[5] = m_ga[0] ^ m_ga[1] ^ m_ga[2] ^ m_ga[3] ^ m_ga[4];
// vme.q_ga = m_ga;
endtask // set_slot
protected task acknowledge_irq(int level, ref int vector);
......@@ -223,7 +224,6 @@ class CBusAccessor_VME64x extends CBusAccessor;
#40ns;
vme.q_addr[3:1] = level;
vme.q_iackin_n = 1'b0;
vme.q_iack_n = 1'b0;
vme.q_am = 'h29;
#100ns;
......@@ -238,7 +238,6 @@ class CBusAccessor_VME64x extends CBusAccessor;
vector = vme.data;
vme.q_iackin_n = 1'b1;
vme.q_iack_n = 1'b1;
#100ns;
release_bus();
......@@ -343,6 +342,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
#40ns;
end // for (i=0;i<_data.size();i++)
#100ns;
release_bus();
endtask // rw_generic
......
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
#top_module = "main"
#sim_tool="modelsim"
files = [ "main.sv" ]
#include_dirs =[".", "../../include", "../../include/vme64x_bfm", "../../include/wb"]
modules = { "local" : [ "../../top/svec/wr" ] }
`timescale 10fs/10fs
`include "acam_model.svh"
`include "tunable_clock_gen.svh"
`include "random_pulse_gen.svh"
`include "jittery_delay.svh"
`include "mc100ep195.vh"
`include "wb/simdrv_defs.svh"
`include "wb/if_wb_master.svh"
`timescale 10fs/10fs
module trivial_spi_gpio(input sclk, cs_n, mosi, output reg [7:0] gpio);
int bit_count = 0;
reg [7:0] sreg;
always@(negedge cs_n)
bit_count <= 0;
always@(posedge sclk)
begin
bit_count <= bit_count + 1;
sreg <= { sreg[6:0], mosi };
end
always@(posedge cs_n)
if(bit_count == 24)
gpio <= sreg[7:0];
initial gpio = 0;
endmodule // trivial_spi
/* Board-level wrapper */
interface IFineDelayFMC;
wire tdc_start_p;
wire tdc_start_n;
wire clk_ref_p;
wire clk_ref_n;
wire trig_a;
wire tdc_cal_pulse;
wire [27:0] tdc_d;
wire tdc_emptyf;
wire tdc_alutrigger;
wire tdc_wr_n;
wire tdc_rd_n;
wire tdc_oe_n;
wire led_trig;
wire tdc_start_dis;
wire tdc_stop_dis;
wire spi_cs_dac_n;
wire spi_cs_pll_n;
wire spi_cs_gpio_n;
wire spi_sclk;
wire spi_mosi;
wire spi_miso;
wire [3:0] delay_len;
wire [9:0] delay_val;
wire [3:0] delay_pulse;
wire dmtd_clk;
wire dmtd_fb_in;
wire dmtd_fb_out;
wire pll_status;
wire ext_rst_n;
wire onewire;
modport board
(
output tdc_start_p, tdc_start_n, clk_ref_p, clk_ref_n, trig_a, spi_miso,
tdc_emptyf, dmtd_fb_in, dmtd_fb_out, pll_status,
input tdc_cal_pulse, tdc_wr_n, tdc_rd_n, tdc_oe_n, tdc_alutrigger, led_trig, tdc_start_dis,
tdc_stop_dis, spi_cs_dac_n, spi_cs_pll_n, spi_cs_gpio_n, spi_sclk, spi_mosi,
delay_len, delay_val, delay_pulse, dmtd_clk, ext_rst_n,
inout onewire, tdc_d);
modport core
(
input tdc_start_p, tdc_start_n, clk_ref_p, clk_ref_n, trig_a, spi_miso,
tdc_emptyf, dmtd_fb_in, dmtd_fb_out, pll_status,
output tdc_cal_pulse, tdc_wr_n, tdc_rd_n, tdc_oe_n, tdc_alutrigger, led_trig, tdc_start_dis,
tdc_stop_dis, spi_cs_dac_n, spi_cs_pll_n, spi_cs_gpio_n, spi_sclk, spi_mosi,
delay_len, delay_val, delay_pulse, dmtd_clk, ext_rst_n,
inout onewire, tdc_d);
endinterface // IFineDelayFMC
module fdelay_board (
input trig_i,
output [3:0] out_o,
IFineDelayFMC.board fmc
);
reg clk_ref_250 = 0;
reg clk_ref_125 = 0;
reg clk_tdc = 0;
reg [3:0] tdc_start_div = 0;
reg tdc_start;
always #(4ns / 2) clk_ref_250 <= ~clk_ref_250;
always@(posedge clk_ref_250) clk_ref_125 <= ~clk_ref_125;
always #(32ns / 2) clk_tdc <= ~clk_tdc;
assign fmc.clk_ref_p = clk_ref_125;
assign fmc.clk_ref_n = ~clk_ref_125;
always@(posedge clk_ref_125) begin
tdc_start_div <= tdc_start_div + 1;
tdc_start <= tdc_start_div[3];
end
assign fmc.tdc_start_p = tdc_start;
assign fmc.tdc_start_n = ~tdc_start;
wire trig_a_muxed;
wire [7:0] spi_gpio_out;
wire trig_cal_sel = 1'b1;
assign trig_a_muxed = (trig_cal_sel ? trig_i : fmc.tdc_cal_pulse);
trivial_spi_gpio
SPI_GPIO (
.sclk(fmc.spi_sclk),
.cs_n(fmc.spi_cs_gpio_n),
.mosi(fmc.spi_mosi),
.gpio(spi_gpio_out));
acam_model
#(
.g_verbose(0)
) ACAM (
.PuResN(fmc.ext_rst_n),
.Alutrigger(fmc.tdc_alutrigger),
.RefClk (clk_tdc),
.WRN(fmc.tdc_wr_n),
.RDN(fmc.tdc_rd_n),
.CSN(1'b0),
.OEN(fmc.tdc_oe_n),
.Adr(spi_gpio_out[3:0]),
.D(fmc.tdc_d),
.DStart(tdc_start_delayed),
.DStop1(trig_a_muxed),
.DStop2(1'b0),
.TStart(1'b0),
.TStop(1'b0),
.StartDis(fmc.tdc_start_dis),
.StopDis(fmc.tdc_stop_dis),
.IrFlag(),
.ErrFlag(),
.EF1 (fmc.tdc_emptyf),
.LF1 ()
);
jittery_delay
#(
.g_delay(3ns),
.g_jitter(10ps)
)
DLY_TRIG
(
.in_i(trig_a_muxed),
.out_o(trig_a_n_delayed)
);
assign fmc.trig_a = trig_a_n_delayed;
jittery_delay
#(
.g_delay(2.2ns),
.g_jitter(10ps)
)
DLY_TDC_START
(
.in_i(tdc_start),
.out_o(tdc_start_delayed)
);
genvar gg;
function bit[9:0] reverse_bits (bit [9:0] x);
reg [9:0] tmp;
int i;
for(i=0;i<10;i++)
tmp[9-i]=x[i];
return tmp;
endfunction // reverse_bits
mc100ep195
U_delay_line0(
.len(fmc.delay_len[0]),
.i(fmc.delay_pulse[0]),
.delay(reverse_bits(fmc.delay_val)),
.o(out_o[0]));
endmodule // main
`define WIRE_FINE_DELAY_PINS(fmc_index,iface) \
.fd``fmc_index``_tdc_start_p_i (iface.core.tdc_start_p), \
.fd``fmc_index``_tdc_start_n_i (iface.core.tdc_start_n), \
.fd``fmc_index``_clk_ref_p_i (iface.core.clk_ref_p), \
.fd``fmc_index``_clk_ref_n_i (iface.core.clk_ref_n), \
.fd``fmc_index``_trig_a_i (iface.core.trig_a), \
.fd``fmc_index``_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fd``fmc_index``_tdc_d_b (iface.core.tdc_d), \
.fd``fmc_index``_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fd``fmc_index``_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fd``fmc_index``_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fd``fmc_index``_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fd``fmc_index``_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fd``fmc_index``_led_trig_o (iface.core.led_trig), \
.fd``fmc_index``_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fd``fmc_index``_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fd``fmc_index``_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fd``fmc_index``_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fd``fmc_index``_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fd``fmc_index``_spi_sclk_o (iface.core.spi_sclk), \
.fd``fmc_index``_spi_mosi_o (iface.core.spi_mosi), \
.fd``fmc_index``_spi_miso_i (iface.core.spi_miso), \
.fd``fmc_index``_delay_len_o (iface.core.delay_len), \
.fd``fmc_index``_delay_val_o (iface.core.delay_val), \
.fd``fmc_index``_delay_pulse_o (iface.core.delay_pulse), \
.fd``fmc_index``_dmtd_clk_o (iface.core.dmtd_clk), \
.fd``fmc_index``_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fd``fmc_index``_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fd``fmc_index``_pll_status_i (iface.core.pll_status), \
.fd``fmc_index``_ext_rst_n_o (iface.core.ext_rst_n), \
.fd``fmc_index``_onewire_b (iface.core.onewire)
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "fdelay_board.svh"
module main;
reg rst_n = 0;
reg clk_125m = 0, clk_20m = 0;
always #4ns clk_125m <= ~clk_125m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20) @(posedge clk_125m);
rst_n = 1;
end
//IFineDelayFMC I_fmc0(), I_fmc1();
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave,8);
`DECLARE_VME_BUFFERS(VME.slave,9);
`DECLARE_VME_BUFFERS(VME.slave,10);
wire daisy_iack,daisy_iack2,daisy_iack3;
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) U_SVEC1 (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.clk_20m_vcxo_i(clk_20m),
.rst_n_i(rst_n),
.VME_IACKIN_n_i(VME.iack_n),
// .VME_IACK_n_i(VME.iack_n),
.VME_IACKOUT_n_o(daisy_iack),
`WIRE_VME_PINS(8)
);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) U_SVEC2 (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.clk_20m_vcxo_i(clk_20m),
.rst_n_i(rst_n),
.VME_IACKIN_n_i(daisy_iack),
// .VME_IACK_n_i(VME.iack_n),
.VME_IACKOUT_n_o(daisy_iack2),
`WIRE_VME_PINS(9)
);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) U_SVEC3 (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.clk_20m_vcxo_i(clk_20m),
.rst_n_i(rst_n),
.VME_IACKIN_n_i(daisy_iack2),
// .VME_IACK_n_i(VME.iack_n),
.VME_IACKOUT_n_o(daisy_iack3),
`WIRE_VME_PINS(10)
);
task automatic config_vme_function(ref CBusAccessor_VME64x acc, input int slot, input int func, uint64_t base, int am);
uint64_t addr = 'h7ff63 + func * 'h10;
uint64_t val = (base) | (am << 2);
acc.set_slot(slot);
$display("Func%d ADER=0x%x", func, val);
acc.write(addr + 0, (val >> 24) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 4, (val >> 16) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 8, (val >> 8) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 12, (val >> 0) & 'hff, CR_CSR|A32|D08Byte3);
endtask // config_vme_function
task automatic enable_vme_core (ref CBusAccessor_VME64x acc, input int slot );
acc.set_slot(slot);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A24 | D32 | SINGLE);
endtask // enable_vme_core
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map slot 8 func1 to 0xc00000, A24 */
config_vme_function(acc, 8, 1, 'hc00000, 'h39);
enable_vme_core(acc, 8);
config_vme_function(acc, 9, 1, 'hc80000, 'h39);
enable_vme_core(acc, 9);
acc.set_default_modifiers(A24 | D32 | SINGLE);
endtask // init_vme64x_core