hdl/testbench: trivial SVEC testbench

3a565b1f · Tomasz Wlostowski · 6216cf6a · 3a565b1f · 3a565b1f · 3a565b1f
Commit 3a565b1f authored Jun 02, 2020 by Tomasz Wlostowski
7 changed files
--- a/hdl/include/timestamp.svh
+++ b/hdl/include/timestamp.svh
 `ifndef __TIMESTAMP_SVH
 `define __TIMESTAMP_SVH

-`include "wb/simdrv_defs.svh"
+`include "simdrv_defs.svh"

 class Timestamp;
   uint64_t utc;

--- a/hdl/testbench/svec_wr_top/Manifest.py
+++ b/hdl/testbench/svec_wr_top/Manifest.py
 ctrls = ["bank3_32b_32b"]
 action = "simulation"
 target = "xilinx"
+vcom_opt="-mixedsvvh l"
 fetchto = "../../ip_cores"
 include_dirs = ["../../include/vme64x_bfm",
-                "../../include/wb", "../../include",
+                "../../include",
                "../../ip_cores/general-cores/modules/wishbone/wb_spi/",
+                "../../ip_cores/general-cores/sim/",
                "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
 syn_device = "xc6slx45t"
 sim_tool = "modelsim"

--- a/hdl/testbench/svec_wr_top/fdelay_board.svh
+++ b/hdl/testbench/svec_wr_top/fdelay_board.svh
@@ -6,8 +6,8 @@
 `include "jittery_delay.svh"
 `include "mc100ep195.vh"

-`include "wb/simdrv_defs.svh"
-`include "wb/if_wb_master.svh"
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"

 `timescale 10fs/10fs


--- a/hdl/testbench/svec_wr_top/main.sv
+++ b/hdl/testbench/svec_wr_top/main.sv
@@ -142,6 +142,13 @@ module main;
      .fmc(I_fmc0.board)
      );

+   fdelay_board U_Board1
+     (
+      .trig_i(trig0),
+      .out_o(),
+      .fmc(I_fmc1.board)
+      );
+
   reg out0_delayed=0;

   always@(out0[0]) out0_delayed <= #10ps out0[0];
@@ -177,13 +184,27 @@ module main;
      init_vme64x_core(acc);
      acc_casted.set_default_xfer_size(A32|SINGLE|D32);

-      
+      $error("Init driver");
      
      drv0 = new(acc, 'h80010000);
      drv0.init();
      drv1 = new(acc, 'h80020000);
      drv1.init();

+      $error("set idelay0");
+      acc.write('h80010080, 10);
+      #20us;
+
+      $error("set idelay1");
+      
+      acc.write('h80020080, 10);
+      #20us;
+
+      $stop;
+      
+      
+      
+
     drv0.set_idelay_taps(5);
      
 /*      t_start=new;    

--- a/hdl/testbench/svec_wr_top/run.do
+++ b/hdl/testbench/svec_wr_top/run.do
-vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
+#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
 vsim -t 1ps work.main -novopt -L unisim

 set StdArithNoWarnings 1

--- a/hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
+++ b/hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
 `include "regs/fd_main_regs.vh"
 `include "regs/fd_channel_regs.vh"

-`include "wb/simdrv_defs.svh"
+`include "simdrv_defs.svh"
 `include "timestamp.svh"

 const int SPI_PLL  = 0;

--- a/hdl/testbench/svec_wr_top/wave.do
+++ b/hdl/testbench/svec_wr_top/wave.do