Commit 605cafb3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

rtl/fd_channel_wishbone_slave: FRR register should be in clk_ref domain

parent e8cf7876
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Thu Jul 4 10:40:48 2013
-- Created : Thu Jul 4 13:50:31 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -64,6 +64,11 @@ signal fd_channel_dcr_force_dly_sync2 : std_logic ;
signal fd_channel_dcr_no_fine_int : std_logic ;
signal fd_channel_dcr_force_hi_int : std_logic ;
signal fd_channel_frr_int : std_logic_vector(9 downto 0);
signal fd_channel_frr_swb : std_logic ;
signal fd_channel_frr_swb_delay : std_logic ;
signal fd_channel_frr_swb_s0 : std_logic ;
signal fd_channel_frr_swb_s1 : std_logic ;
signal fd_channel_frr_swb_s2 : std_logic ;
signal fd_channel_u_starth_int : std_logic_vector(7 downto 0);
signal fd_channel_u_startl_int : std_logic_vector(31 downto 0);
signal fd_channel_c_start_int : std_logic_vector(27 downto 0);
......@@ -115,6 +120,8 @@ begin
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_frr_swb <= '0';
fd_channel_frr_swb_delay <= '0';
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
fd_channel_c_start_int <= "0000000000000000000000000000";
......@@ -142,6 +149,8 @@ begin
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_frr_swb <= fd_channel_frr_swb_delay;
fd_channel_frr_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -196,6 +205,8 @@ begin
when "0001" =>
if (wb_we_i = '1') then
fd_channel_frr_int <= wrdata_reg(9 downto 0);
fd_channel_frr_swb <= '1';
fd_channel_frr_swb_delay <= '1';
end if;
rddata_reg(9 downto 0) <= fd_channel_frr_int;
rddata_reg(10) <= 'X';
......@@ -220,7 +231,7 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
......@@ -586,7 +597,25 @@ begin
-- Force output high
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine range in SY89825 taps.
regs_o.frr_o <= fd_channel_frr_int;
-- asynchronous std_logic_vector register : Fine range in SY89825 taps. (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_frr_swb_s0 <= '0';
fd_channel_frr_swb_s1 <= '0';
fd_channel_frr_swb_s2 <= '0';
regs_o.frr_o <= "0000000000";
elsif rising_edge(clk_ref_i) then
fd_channel_frr_swb_s0 <= fd_channel_frr_swb;
fd_channel_frr_swb_s1 <= fd_channel_frr_swb_s0;
fd_channel_frr_swb_s2 <= fd_channel_frr_swb_s1;
if ((fd_channel_frr_swb_s2 = '0') and (fd_channel_frr_swb_s1 = '1')) then
regs_o.frr_o <= fd_channel_frr_int;
end if;
end if;
end process;
-- TAI seconds (MSB)
regs_o.u_starth_o <= fd_channel_u_starth_int;
-- TAI seconds (LSB)
......
......@@ -162,6 +162,7 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns, width/sp
field {
name = "Fine range in SY89825 taps.";
clock = "clk_ref_i";
size = 10;
type = SLV;
access_bus = READ_WRITE;
......
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