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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
6192e6db
Commit
6192e6db
authored
Sep 11, 2019
by
Tomasz Wlostowski
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top/spec: SPEC top level compliant with The Convention
parent
b29188b3
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5 changed files
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715 additions
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1419 deletions
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-1419
Manifest.py
hdl/top/spec/Manifest.py
+11
-4
spec_reset_gen.vhd
hdl/top/spec/spec_reset_gen.vhd
+0
-55
spec_top.ucf
hdl/top/spec/spec_top.ucf
+204
-456
spec_top.vhd
hdl/top/spec/spec_top.vhd
+500
-847
synthesis_descriptor.vhd
hdl/top/spec/synthesis_descriptor.vhd
+0
-57
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hdl/top/spec/Manifest.py
View file @
6192e6db
files
=
[
"s
ynthesis_descriptor.vhd"
,
"spec_top.vhd"
,
"spec_top.ucf"
,
"spec_reset_gen.vhd
"
]
files
=
[
"s
pec_top.vhd"
,
"spec_top.ucf
"
]
fetchto
=
"../../ip_cores"
modules
=
{
"local"
:
[
"../../rtl"
,
"../../platform"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git"
]
"local"
:
[
"../../rtl"
,
"../../platform"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
,
"../../ip_cores/wr-cores/board/spec"
,
"../../ip_cores/gn4124-core"
,
"../../ip_cores/spec"
,
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_reset_gen.vhd
deleted
100644 → 0
View file @
b29188b3
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
NUMERIC_STD
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
spec_reset_gen
is
port
(
clk_sys_i
:
in
std_logic
;
rst_pcie_n_a_i
:
in
std_logic
;
rst_button_n_a_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
);
end
spec_reset_gen
;
architecture
behavioral
of
spec_reset_gen
is
signal
powerup_cnt
:
unsigned
(
7
downto
0
)
:
=
x"00"
;
signal
button_synced_n
:
std_logic
;
signal
pcie_synced_n
:
std_logic
;
signal
powerup_n
:
std_logic
:
=
'0'
;
begin
-- behavioral
U_EdgeDet_PCIe
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
'1'
,
data_i
=>
rst_pcie_n_a_i
,
ppulse_o
=>
pcie_synced_n
);
U_Sync_Button
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
'1'
,
data_i
=>
rst_button_n_a_i
,
synced_o
=>
button_synced_n
);
p_powerup_reset
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
powerup_cnt
/=
x"ff"
)
then
powerup_cnt
<=
powerup_cnt
+
1
;
powerup_n
<=
'0'
;
else
powerup_n
<=
'1'
;
end
if
;
end
if
;
end
process
;
rst_n_o
<=
powerup_n
and
button_synced_n
and
(
not
pcie_synced_n
);
end
behavioral
;
hdl/top/spec/spec_top.ucf
View file @
6192e6db
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hdl/top/spec/spec_top.vhd
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6192e6db
This diff is collapsed.
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hdl/top/spec/synthesis_descriptor.vhd
deleted
100644 → 0
View file @
b29188b3
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"spec-fine-delay "
,
syn_commit_id
=>
"7dd0a8c348dee0a3a660143c80487a8a"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"20141209"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end
package
synthesis_descriptor
;
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