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FMC DEL 1ns 4cha
Commit 6216cf6a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: extends IODELAY N_TAPS register to 8 bits

parent b362e383
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Showing with 10 additions and 12 deletions
hdl/include/regs/fd_main_regs.vh
View file @ 6216cf6a
......@@ -162,7 +162,7 @@
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define FD_IODELAY_ADJ_N_TAPS 32'h000000ff
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 6216cf6a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Tue Oct 22 18:06:55 2019
-- Created : Thu May 28 16:19:19 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -57,7 +57,7 @@ package fd_main_wbgen2_pkg is
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
fmc_slot_id_slot_id_i : std_logic_vector(3 downto 0);
iodelay_adj_n_taps_i : std_logic_vector(5 downto 0);
iodelay_adj_n_taps_i : std_logic_vector(7 downto 0);
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
......@@ -157,7 +157,7 @@ package fd_main_wbgen2_pkg is
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
iodelay_adj_n_taps_o : std_logic_vector(5 downto 0);
iodelay_adj_n_taps_o : std_logic_vector(7 downto 0);
iodelay_adj_n_taps_load_o : std_logic;
end record;
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 6216cf6a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Tue Oct 22 18:06:55 2019
-- Created : Thu May 28 16:19:19 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -1219,9 +1219,7 @@ begin
if (wb_we_i = '1') then
regs_o.iodelay_adj_n_taps_load_o <= '1';
end if;
rddata_reg(5 downto 0) <= regs_i.iodelay_adj_n_taps_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(7 downto 0) <= regs_i.iodelay_adj_n_taps_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -2114,7 +2112,7 @@ end process;
-- Slot ID
-- Number of delay line taps.
regs_o.iodelay_adj_n_taps_o <= wrdata_reg(5 downto 0);
regs_o.iodelay_adj_n_taps_o <= wrdata_reg(7 downto 0);
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 6216cf6a
......@@ -1065,7 +1065,7 @@ peripheral {
name = "Number of delay line taps.";
prefix = "N_TAPS";
type = SLV;
size = 6;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
......
hdl/rtl/fine_delay_core.vhd
View file @ 6216cf6a
......@@ -368,8 +368,8 @@ architecture rtl of fine_delay_core is
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
signal iodelay_ntaps : std_logic_vector(5 downto 0);
signal iodelay_cnt : unsigned(5 downto 0);
signal iodelay_ntaps : std_logic_vector(7 downto 0);
signal iodelay_cnt : unsigned(7 downto 0);
signal iodelay_div : unsigned(6 downto 0);
signal iodelay_tick : std_logic;
signal iodelay_cal_done : std_logic;
......
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