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FMC DEL 1ns 4cha
Commit 9cc135fb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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syn/top: SPEC non-whiterabbit top level updated for V3

parent 6f48bd55
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Showing with 572 additions and 422 deletions
hdl/syn/spec/non_wr/Manifest.py
View file @ 9cc135fb
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
......@@ -9,4 +9,4 @@ syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
modules = { "local" : [ "../../top/spec_1_1" ] }
modules = { "local" : [ "../../../top/spec/non_wr", "../../../platform" ] }
hdl/syn/spec/non_wr/spec_fine_delay.xise
View file @ 9cc135fb
......@@ -89,6 +89,7 @@
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -121,7 +122,7 @@
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
......@@ -241,7 +242,6 @@
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -339,627 +339,720 @@
</libraries>
<files>
<file xil_pn:name="../../top/spec_1_1/spec_top.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../top/spec/non_wr/spec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="fifo_generator_v6_1"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../rtl/fd_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
hdl/top/spec/non_wr/Manifest.py
View file @ 9cc135fb
files = [
"spec_top.vhd",
"spec_top.ucf",
#"wb_gpio_port_notristates.vhd"
"spec_serial_dac.vhd",
"spec_serial_dac_arb.vhd"
];
fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
modules = {"local" : "../../rtl",
"svn" : "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" }
\ No newline at end of file
modules = {"local" : [ "../../../rtl", "../../../platform" ],
"svn" : "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" }
hdl/top/spec/non_wr/spec_top.ucf
View file @ 9cc135fb
......@@ -26,10 +26,10 @@ NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
......@@ -154,6 +154,9 @@ NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
#
# Fine Delay V3 Pin definitions
#
NET "fd_clk_ref_n_i" LOC = L22 ;
......@@ -210,18 +213,18 @@ NET "fd_spi_mosi_o" LOC = AA18 ;
NET "fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_sclk_o" LOC = Y17 ;
NET "fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[0]" LOC = T12 ;
NET "fd_tdc_a_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[1]" LOC = U12 ;
NET "fd_tdc_a_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[2]" LOC = Y15 ;
NET "fd_tdc_a_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[3]" LOC = AB15 ;
NET "fd_tdc_a_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_clk_o" LOC = T12 ;
NET "fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_out_i" LOC = U12 ;
NET "fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fd_pll_status_i" LOC = AB15 ;
NET "fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_alutrigger_o" LOC = W12 ;
NET "fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cs_n_o" LOC = T11 ;
NET "fd_tdc_cs_n_o" IOSTANDARD =LVCMOS25;
NET "fd_ext_rst_n_o" LOC = T11 ;
NET "fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[0]" LOC = AB12 ;
NET "fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[1]" LOC = U8 ;
......@@ -296,17 +299,33 @@ NET "fd_tdc_wr_n_o" LOC = Y13 ;
NET "fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fd_trig_a_i" LOC = Y11 ;
NET "fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fd_trig_cal_o" LOC = AB11 ;
NET "fd_trig_cal_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#NET "onewire_b" LOC = W11 ;
#NET "onewire_b" IOSTANDARD =LVCMOS25;
NET "L_CLKp" TNM_NET = "l_clkp_grp";
NET "onewire_b" LOC = W11 ;
NET "onewire_b" IOSTANDARD =LVCMOS25;
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "L_CLKp" TNM_NET = "l_clkp_grp";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
# System clock
......@@ -326,9 +345,9 @@ NET "fd_clk_ref_n_i" TNM_NET = fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fd_clk_ref_p_i" TNM_NET = fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fd_clk_ref_p_i" 8 ns HIGH 50%;
NET "L_CLKn" TNM_NET = L_CLKn;
#NET "L_CLKn" TNM_NET = L_CLKn;
#>DISABLED<#TIMESPEC TS_L_CLKn = PERIOD "L_CLKn" 5 ns HIGH 50%;
NET "L_CLKp" TNM_NET = L_CLKp;
#NET "L_CLKp" TNM_NET = L_CLKp;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/09/06
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
NET "clk_sys" TNM_NET = clk_sys;
......
hdl/top/spec/non_wr/spec_top.vhd
View file @ 9cc135fb
-------------------------------------------------------------------------------
-- Title : Fine Delay Demo (non WR) - SPEC version
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : spec_top.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-26
-- Platform : Xilinx Spartan-6 (XC6SLX45T)
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the Fine Delay Generator FMC core example design
-- for SPEC 1.1+ carriers.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -26,8 +65,8 @@ entity spec_top is
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
-- L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
-- L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
......@@ -67,6 +106,10 @@ entity spec_top is
LED_RED : out std_logic;
LED_GREEN : out std_logic;
-------------------------------------------------------------------------
-- Fine Delay FMC I/Os
-------------------------------------------------------------------------
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
......@@ -74,12 +117,10 @@ entity spec_top is
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic;
fd_trig_cal_o : out std_logic;
fd_tdc_cal_pulse_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_a_o : out std_logic_vector(3 downto 0);
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_cs_n_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
......@@ -96,50 +137,46 @@ entity spec_top is
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd_dmtd_clk_o : out std_logic;
fd_dmtd_fb_in_i : in std_logic;
fd_dmtd_fb_out_i : in std_logic;
fd_pll_status_i : in std_logic;
fd_ext_rst_n_o : out std_logic;
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
onewire_b : inout std_logic
onewire_b : inout std_logic;
-- SPEC DACs
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
component spec_gbit_tester
component spec_serial_dac_arb
generic (
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_ref_gtp0_i : in std_logic;
clk_ref_gtp1_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sata1_txp_o : out std_logic;
sata1_txn_o : out std_logic;
sata1_rxp_i : in std_logic;
sata1_rxn_i : in std_logic;
sata2_txp_o : out std_logic;
sata2_txn_o : out std_logic;
sata2_rxp_i : in std_logic;
sata2_rxn_i : in std_logic;
fmc_txp_o : out std_logic;
fmc_txn_o : out std_logic;
fmc_rxp_i : in std_logic;
fmc_rxn_i : in std_logic;
fmc_gbtclk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
component gn4124_core
generic(
-- g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
......@@ -227,6 +264,87 @@ architecture rtl of spec_top is
);
end component; -- gn4124_core
component fd_ddr_pll
port (
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
component fine_delay_core
generic (
g_with_wr_core : boolean := false;
g_simulation : boolean := false;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_ref_0_i : in std_logic;
clk_ref_180_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
dcm_reset_o : out std_logic;
dcm_locked_i : in std_logic;
trig_a_i : in std_logic;
tdc_cal_pulse_o : out std_logic;
tdc_start_i : in std_logic;
dmtd_fb_in_i : in std_logic;
dmtd_fb_out_i : in std_logic;
dmtd_samp_o : out std_logic;
led_trig_o : out std_logic;
ext_rst_n_o : out std_logic;
pll_status_i : in std_logic;
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
tm_link_up_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tm_utc_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic := '0';
tm_clk_dmtd_locked_i : in std_logic := '0';
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_wr_i : in std_logic := '0';
dmtd_dac_value_o : out std_logic_vector(23 downto 0);
dmtd_dac_wr_o : out std_logic;
owr_en_o : out std_logic;
owr_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector((c_wishbone_data_width+7)/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Constants declaration
......@@ -305,81 +423,28 @@ architecture rtl of spec_top is
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
constant c_NUM_WISHBONE_DEVS : integer := 3;
signal cnx_slave_in : t_wishbone_slave_in;
signal cnx_slave_out : t_wishbone_slave_out;
signal cnx_out : t_wishbone_master_out_array (0 to c_NUM_WISHBONE_DEVS-1);
signal cnx_in : t_wishbone_master_in_array (0 to c_NUM_WISHBONE_DEVS-1);
signal cnx_slave_in : t_wishbone_slave_in_array(0 to 0);
signal cnx_slave_out : t_wishbone_slave_out_array(0 to 0);
signal fd_clk_ref : std_logic;
signal fd_tdc_start : std_logic;
signal onewire_en : std_logic;
component fine_delay_core
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
tm_time_valid_i : in std_logic := '0';
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tm_utc_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic := '0';
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_wr_i : in std_logic := '0';
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
end component;
signal dcm_clk_fb, dcm_clk_ref_0, dcm_clk_ref_180 : std_logic;
signal dcm_clk_ref_0_int, dcm_clk_ref_180_int : std_logic;
signal rst_n : std_logic;
signal powerup_rst_counter : std_logic_vector(10 downto 0) := "00000000000";
signal powerup_rst_counter : std_logic_vector(10 downto 0) := "00000000000";
signal dcm_reset_n, dcm_reset, dcm_locked : std_logic;
signal ddr_pll_reset : std_logic;
signal ddr_pll_locked, fd_pll_status : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(23 downto 0);
begin
process(clk_sys)
......@@ -391,37 +456,18 @@ begin
rst_n <= powerup_rst_counter(0);
--cmp_sys_clk_pll : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "INTERNAL",
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT => 8,
-- CLKFBOUT_PHASE => 0.000,
-- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DIVIDE => 16, -- 125 MHz
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 16,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKIN_PERIOD => 8.0,
-- REF_JITTER => 0.016)
-- port map (
-- CLKFBOUT => pllout_clk_fb_pllref,
-- CLKOUT0 => pllout_clk_sys,
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => open,
-- RST => '0',
-- CLKFBIN => pllout_clk_fb_pllref,
-- CLKIN => clk_125m_pllref);
U_DDR_PLL : fd_ddr_pll
port map (
RST => ddr_pll_reset,
LOCKED => ddr_pll_locked,
CLK_IN1_P => fd_clk_ref_p_i,
CLK_IN1_N => fd_clk_ref_n_i,
CLK_OUT1 => dcm_clk_ref_0,
CLK_OUT2 => dcm_clk_ref_180);
ddr_pll_reset <= not fd_pll_status_i;
fd_pll_status <= fd_pll_status_i and ddr_pll_locked;
cmp_dmtd_clk_pll : PLL_BASE
generic map (
......@@ -467,31 +513,6 @@ begin
O => clk_dmtd,
I => pllout_clk_dmtd);
--cmp_clk_vcxo : BUFG
-- port map (
-- O => clk_20m_vcxo_buf,
-- I => clk_20m_vcxo_i);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
......@@ -508,7 +529,7 @@ begin
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH,
g_CSR_WB_MODE => "classic"
g_CSR_WB_MODE => "pipelined"
)
port map
(
......@@ -565,14 +586,15 @@ begin
---------------------------------------------------------
-- Target Interface (Wishbone master)
wb_clk_i => clk_sys,
wb_adr_o => cnx_slave_in.adr(18 downto 0),
wb_dat_o => cnx_slave_in.dat,
wb_sel_o => cnx_slave_in.sel,
wb_stb_o => cnx_slave_in.stb,
wb_we_o => cnx_slave_in.we,
wb_cyc_o(0) => cnx_slave_in.cyc,
wb_dat_i => cnx_slave_out.dat,
wb_ack_i(0) => cnx_slave_out.ack,
wb_adr_o => cnx_slave_in(0).adr(18 downto 0),
wb_dat_o => cnx_slave_in(0).dat,
wb_sel_o => cnx_slave_in(0).sel,
wb_stb_o => cnx_slave_in(0).stb,
wb_we_o => cnx_slave_in(0).we,
wb_cyc_o(0) => cnx_slave_in(0).cyc,
wb_dat_i => cnx_slave_out(0).dat,
wb_ack_i(0) => cnx_slave_out(0).ack,
-- wb_stall_i(0) => cnx_slave_out(0).stall,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
......@@ -626,57 +648,41 @@ begin
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
U_Fanout : xwb_bus_fanout
generic map (
g_num_outputs => c_NUM_WISHBONE_DEVS,
g_bits_per_slave => 8)
U_DELAY_CORE : fine_delay_core
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_in,
master_o => cnx_out);
cnx_in(2).int <= '0';
cnx_in(2).ack <= '1';
cnx_in(2).rty <= '0';
cnx_in(2).err <= '0';
clk_ref_0_i => dcm_clk_ref_0,
clk_ref_180_i => dcm_clk_ref_180,
clk_sys_i => clk_sys,
clk_dmtd_i => pllout_clk_dmtd,
cnx_in(0).int <= '0';
cnx_in(0).ack <= '1';
cnx_in(0).rty <= '0';
cnx_in(0).err <= '0';
tdc_start_i => fd_tdc_start,
dcm_reset_o => dcm_reset,
dcm_locked_i => dcm_locked,
rst_n_i => RST_N,
trig_a_i => fd_trig_a_i,
tdc_cal_pulse_o => fd_tdc_cal_pulse_o,
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
U_DELAY_CORE : fine_delay_core
port map (
clk_ref_i => fd_clk_ref,
tdc_start_i => fd_tdc_start,
clk_sys_i => clk_sys,
rst_n_i => RST_N,
trig_a_n_i => fd_trig_a_i,
trig_cal_o => fd_trig_cal_o,
led_trig_o => fd_led_trig_o,
acam_a_o => fd_tdc_a_o,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_err_i => '0',
acam_int_i => '0',
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_cs_n_o => fd_tdc_cs_n_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
tm_time_valid_i=>'0',
dmtd_fb_out_i => fd_dmtd_fb_out_i,
dmtd_fb_in_i => fd_dmtd_fb_in_i,
dmtd_samp_o => fd_dmtd_clk_o,
pll_status_i => fd_pll_status,
ext_rst_n_o => fd_ext_rst_n_o,
tm_time_valid_i => '0',
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
......@@ -694,21 +700,52 @@ begin
i2c_sda_oen_o => sda_pad_oen,
owr_i => onewire_b,
owr_en_o => onewire_en,
wb_adr_i => cnx_out(1).adr(7 downto 0),
wb_dat_i => cnx_out(1).dat,
wb_dat_o => cnx_in(1).dat,
wb_cyc_i => cnx_out(1).cyc,
wb_stb_i => cnx_out(1).stb,
wb_we_i => cnx_out(1).we,
wb_ack_o => cnx_in(1).ack);
wb_adr_i => cnx_slave_in(0).adr,
wb_dat_i => cnx_slave_in(0).dat,
wb_dat_o => cnx_slave_out(0).dat,
wb_sel_i => x"f",
wb_cyc_i => cnx_slave_in(0).cyc,
wb_stb_i => cnx_slave_in(0).stb,
wb_we_i => cnx_slave_in(0).we,
wb_ack_o => cnx_slave_out(0).ack,
wb_stall_o => cnx_slave_out(0).stall,
dmtd_dac_value_o => dac_hpll_data,
dmtd_dac_wr_o => dac_hpll_load_p1
);
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
onewire_b <= '0' when onewire_en = '0' else 'Z';
onewire_b <= '0' when onewire_en = '1' else 'Z';
-- Control of DMTD VCXO DAC
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => RST_N,
val1_i => x"0000",
load1_i => '0',
val2_i => dac_hpll_data(15 downto 0),
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
end rtl;
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