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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
ddbf6ec0
Commit
ddbf6ec0
authored
Sep 09, 2013
by
Tomasz Wlostowski
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hdl/top/spec/wr/spec_top.vhd: updated to the multi-aux clock WR core
parent
605cafb3
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spec_top.vhd
hdl/top/spec/wr/spec_top.vhd
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hdl/top/spec/wr/spec_top.vhd
View file @
ddbf6ec0
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-0
5-29
-- Last update: 2013-0
7-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -623,8 +623,8 @@ begin
g_dpram_initf
=>
"none"
,
g_dpram_size
=>
90112
/
4
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
)
--
g_softpll_enable_debugger => false)
g_address_granularity
=>
BYTE
,
g_softpll_enable_debugger
=>
false
)
port
map
(
clk_sys_i
=>
clk_sys
,
clk_dmtd_i
=>
clk_dmtd
,
...
...
@@ -682,9 +682,9 @@ begin
tm_link_up_o
=>
tm_link_up
,
tm_dac_value_o
=>
tm_dac_value
,
tm_dac_wr_o
=>
tm_dac_wr
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked
,
tm_dac_wr_o
(
0
)
=>
tm_dac_wr
,
tm_clk_aux_lock_en_i
(
0
)
=>
tm_clk_aux_lock_en
,
tm_clk_aux_locked_o
(
0
)
=>
tm_clk_aux_locked
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_utc
,
tm_cycles_o
=>
tm_cycles
,
...
...
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