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FMC DEL 1ns 4cha
Commit e8824c55 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/spec/wr: WR-enabled SPEC top-level

parent 5a31f5c9
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hdl/top/spec/wr/Manifest.py
View file @ e8824c55
......@@ -3,8 +3,7 @@ files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../../rtl",
"../../../../../wr-repos/wr-hdl/modules/mini_bone",
"../../../../../wr-repos/wr-hdl"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
"local" : ["../../../rtl", "../../../platform", "mini_bone" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl" ]
}
hdl/top/spec/wr/spec_top.ucf
View file @ e8824c55
......@@ -2,45 +2,225 @@
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#####################################################################
### SPEC Generic Stuff
#####################################################################
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_PRSNT_M2C_L_i" LOC="AB14";
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
####################################################################################
# FineDelay V3/V4 pins
####################################################################################
NET "fd_clk_ref_n_i" LOC = L22 ;
NET "fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fd_clk_ref_p_i" LOC = L20 ;
NET "fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fd_delay_len_o[0]" LOC = W14 ;
NET "fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[1]" LOC = Y14 ;
NET "fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[2]" LOC = Y18 ;
NET "fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[3]" LOC = W17 ;
NET "fd_delay_len_o[3]" LOC = W14 ;
NET "fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[0]" LOC = W13 ;
NET "fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[1]" LOC = V13 ;
NET "fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[2]" LOC = U15 ;
NET "fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[3]" LOC = T15 ;
NET "fd_delay_len_o[2]" LOC = Y14 ;
NET "fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[1]" LOC = Y18 ;
NET "fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[0]" LOC = W17 ;
NET "fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[3]" LOC = W13 ;
NET "fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[2]" LOC = V13 ;
NET "fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[1]" LOC = U15 ;
NET "fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[0]" LOC = T15 ;
NET "fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" LOC = A20 ;
NET "fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[1]" LOC = B20 ;
......@@ -75,18 +255,18 @@ NET "fd_spi_mosi_o" LOC = AA18 ;
NET "fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_sclk_o" LOC = Y17 ;
NET "fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[0]" LOC = T12 ;
NET "fd_tdc_a_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[1]" LOC = U12 ;
NET "fd_tdc_a_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[2]" LOC = Y15 ;
NET "fd_tdc_a_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[3]" LOC = AB15 ;
NET "fd_tdc_a_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_clk_o" LOC = T12 ;
NET "fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_out_i" LOC = U12 ;
NET "fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fd_pll_status_i" LOC = AB15 ;
NET "fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_alutrigger_o" LOC = W12 ;
NET "fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cs_n_o" LOC = T11 ;
NET "fd_tdc_cs_n_o" IOSTANDARD =LVCMOS25;
NET "fd_ext_rst_n_o" LOC = T11 ;
NET "fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[0]" LOC = AB12 ;
NET "fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[1]" LOC = U8 ;
......@@ -161,388 +341,21 @@ NET "fd_tdc_wr_n_o" LOC = Y13 ;
NET "fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fd_trig_a_i" LOC = Y11 ;
NET "fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fd_trig_cal_o" LOC = AB11 ;
NET "fd_trig_cal_o" IOSTANDARD =LVCMOS25;
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#NET "onewire_b" LOC = W11 ;
#NET "onewire_b" IOSTANDARD =LVCMOS25;
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = F17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = C17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxn_i" LOC= C15;
#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;
#NET "wr_ref_clk_p_i" LOC=C11;
#NET "wr_ref_clk_n_i" LOC=D11;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
#NET "LA00_N" LOC = AB11;
#NET "LA00_N" IOSTANDARD = "LVCMOS25";
#NET "LA00_P" LOC = Y11;
#NET "LA00_P" IOSTANDARD = "LVCMOS25";
#NET "LA01_N" LOC = AB12;
#NET "LA01_N" IOSTANDARD = "LVCMOS25";
#NET "LA01_P" LOC = AA12;
#NET "LA01_P" IOSTANDARD = "LVCMOS25";
#NET "sda1_b" LOC = Y6;
#NET "sda1_b" IOSTANDARD = "LVCMOS25";
#NET "scl1_b" LOC = W6;
#NET "scl1_b" IOSTANDARD = "LVCMOS25";
#NET "LA02_N" LOC = Y6;
#NET "LA02_N" IOSTANDARD = "LVCMOS25";
#NET "LA02_P" LOC = W6;
#NET "LA02_P" IOSTANDARD = "LVCMOS25";
#NET "LA03_N" LOC = W8;
#NET "LA03_N" IOSTANDARD = "LVCMOS25";
#NET "LA03_P" LOC = V7;
##NET "LA03_P" IOSTANDARD = "LVCMOS25";
#NET "LA04_N" LOC = U8;
#NET "LA04_N" IOSTANDARD = "LVCMOS25";
#NET "LA04_P" LOC = T8;
#NET "LA04_P" IOSTANDARD = "LVCMOS25";
#NET "LA05_N" LOC = AB6;
#NET "LA05_N" IOSTANDARD = "LVCMOS25";
#NET "LA05_P" LOC = AA6;
#NET "LA05_P" IOSTANDARD = "LVCMOS25";
#NET "LA06_N" LOC = AB5;
#NET "LA06_N" IOSTANDARD = "LVCMOS25";
#NET "LA06_P" LOC = Y5;
#NET "LA06_P" IOSTANDARD = "LVCMOS25";
#NET "LA07_N" LOC = V9;
#NET "LA07_N" IOSTANDARD = "LVCMOS25";
#NET "LA07_P" LOC = U9;
#NET "LA07_P" IOSTANDARD = "LVCMOS25";
#NET "LA08_N" LOC = R8;
#NET "LA08_N" IOSTANDARD = "LVCMOS25";
#NET "LA08_P" LOC = R9;
#NET "LA08_P" IOSTANDARD = "LVCMOS25";
#NET "LA09_N" LOC = AB7;
#NET "LA09_N" IOSTANDARD = "LVCMOS25";
#NET "LA09_P" LOC = Y7;
#NET "LA09_P" IOSTANDARD = "LVCMOS25";
#NET "LA10_N" LOC = AB8;
#NET "LA10_N" IOSTANDARD = "LVCMOS25";
#NET "LA10_P" LOC = AA8;
#NET "LA10_P" IOSTANDARD = "LVCMOS25";
#NET "LA11_N" LOC = Y10;
#NET "LA11_N" IOSTANDARD = "LVCMOS25";
#NET "LA11_P" LOC = W10;
#NET "LA11_P" IOSTANDARD = "LVCMOS25";
#NET "LA12_N" LOC = U10;
#NET "LA12_N" IOSTANDARD = "LVCMOS25";
#NET "LA12_P" LOC = T10;
#NET "LA12_P" IOSTANDARD = "LVCMOS25";
#NET "LA13_N" LOC = AB9;
#NET "LA13_N" IOSTANDARD = "LVCMOS25";
#NET "LA13_P" LOC = Y9;
#NET "LA13_P" IOSTANDARD = "LVCMOS25";
#NET "LA14_N" LOC = AB4;
#NET "LA14_N" IOSTANDARD = "LVCMOS25";
#NET "LA14_P" LOC = AA4;
#NET "LA14_P" IOSTANDARD = "LVCMOS25";
#NET "LA15_N" LOC = W11;
#NET "LA15_N" IOSTANDARD = "LVCMOS25";
#NET "LA15_P" LOC = V11;
#NET "LA15_P" IOSTANDARD = "LVCMOS25";
#NET "LA16_N" LOC = AB15;
#NET "LA16_N" IOSTANDARD = "LVCMOS25";
#NET "LA16_P" LOC = Y15;
#NET "LA16_P" IOSTANDARD = "LVCMOS25";
#NET "LA17_N" LOC = AB13;
#NET "LA17_N" IOSTANDARD = "LVCMOS25";
#NET "LA17_P" LOC = Y13;
#NET "LA17_P" IOSTANDARD = "LVCMOS25";
#NET "LA18_N" LOC = U12;
#NET "LA18_N" IOSTANDARD = "LVCMOS25";
#NET "LA18_P" LOC = T12;
#NET "LA18_P" IOSTANDARD = "LVCMOS25";
#NET "LA19_N" LOC = Y12;
#NET "LA19_N" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = W12;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA20_N" LOC = T11;
#NET "LA20_N" IOSTANDARD = "LVCMOS25";
#NET "LA20_P" LOC = R11;
#NET "LA20_P" IOSTANDARD = "LVCMOS25";
#NET "LA21_N" LOC = W13;
#NET "LA21_N" IOSTANDARD = "LVCMOS25";
#NET "LA21_P" LOC = V13;
#NET "LA21_P" IOSTANDARD = "LVCMOS25";
#NET "LA22_N" LOC = T14;
#NET "LA22_N" IOSTANDARD = "LVCMOS25";
#NET "LA22_P" LOC = R13;
#NET "LA22_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA24_N" LOC = Y14;
#NET "LA24_N" IOSTANDARD = "LVCMOS25";
#NET "LA24_P" LOC = W14;
#NET "LA24_P" IOSTANDARD = "LVCMOS25";
#NET "LA25_N" LOC = U15;
#NET "LA25_N" IOSTANDARD = "LVCMOS25";
#NET "LA25_P" LOC = T15;
#NET "LA25_P" IOSTANDARD = "LVCMOS25";
#NET "LA26_N" LOC = AB17;
#NET "LA26_N" IOSTANDARD = "LVCMOS25";
#NET "LA26_P" LOC = Y17;
#NET "LA26_P" IOSTANDARD = "LVCMOS25";
#NET "LA27_N" LOC = AB18;
#NET "LA27_N" IOSTANDARD = "LVCMOS25";
#NET "LA27_P" LOC = AA18;
#NET "LA27_P" IOSTANDARD = "LVCMOS25";
#NET "LA28_N" LOC = W15;
#NET "LA28_N" IOSTANDARD = "LVCMOS25";
#NET "LA28_P" LOC = Y16;
#NET "LA28_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "LA29_P" LOC = W17;
#NET "LA29_P" IOSTANDARD = "LVCMOS25";
#NET "LA30_N" LOC = W18;
#NET "LA30_N" IOSTANDARD = "LVCMOS25";
#NET "LA30_P" LOC = V17;
#NET "LA30_P" IOSTANDARD = "LVCMOS25";
#NET "LA31_N" LOC = C18;
#NET "LA31_N" IOSTANDARD = "LVCMOS25";
#NET "LA31_P" LOC = D17;
#NET "LA31_P" IOSTANDARD = "LVCMOS25";
#NET "LA32_N" LOC = A20;
#NET "LA32_N" IOSTANDARD = "LVCMOS25";
#NET "LA32_P" LOC = B20;
#NET "LA32_P" IOSTANDARD = "LVCMOS25";
#NET "LA33_N" LOC = A19;
#NET "LA33_N" IOSTANDARD = "LVCMOS25";
#NET "LA33_P" LOC = C19;
#NET "LA33_P" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SCL" LOC = AA14;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = AB14;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";#NET "DDR3_CAS_N" LOC = M4;
#NET "DDR3_CAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_N" LOC = K3;
#NET "DDR3_CK_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_P" LOC = K4;
#NET "DDR3_CK_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CKE" LOC = F2;
#NET "DDR3_CKE" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDM" LOC = N4;
#NET "DDR3_LDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_N" LOC = N1;
#NET "DDR3_LDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_P" LOC = N3;
#NET "DDR3_LDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_ODT" LOC = L6;
#NET "DDR3_ODT" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RAS_N" LOC = M5;
#NET "DDR3_RAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RESET_N" LOC = E3;
#NET "DDR3_RESET_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDM" LOC = P3;
#NET "DDR3_UDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_N" LOC = V1;
#NET "DDR3_UDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_P" LOC = V2;
#NET "DDR3_UDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_WE_N" LOC = H2;
#NET "DDR3_WE_N" IOSTANDARD = "LVCMOS15";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
#NET "PCB_VER[0]" LOC = P5;
#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[1]" LOC = P4;
#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[2]" LOC = AA2;
#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[3]" LOC = AA1;
#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[4]" LOC = N6;
#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[5]" LOC = N7;
#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[6]" LOC = U4;
#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[7]" LOC = T4;
#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A0" LOC = K2;
#NET "DDR3_A0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A1" LOC = K1;
#NET "DDR3_A1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A2" LOC = K5;
#NET "DDR3_A2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A3" LOC = M6;
#NET "DDR3_A3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A4" LOC = H3;
#NET "DDR3_A4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A5" LOC = M3;
#NET "DDR3_A5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A6" LOC = L4;
#NET "DDR3_A6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A7" LOC = K6;
#NET "DDR3_A7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A8" LOC = G3;
#NET "DDR3_A8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A9" LOC = G1;
#NET "DDR3_A9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A10" LOC = J4;
#NET "DDR3_A10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A11" LOC = E1;
#NET "DDR3_A11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A12" LOC = F1;
#NET "DDR3_A12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A13" LOC = J6;
#NET "DDR3_A13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A14" LOC = H5;
#NET "DDR3_A14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA0" LOC = J3;
#NET "DDR3_BA0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA1" LOC = J1;
#NET "DDR3_BA1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA2" LOC = H1;
#NET "DDR3_BA2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ0" LOC = R3;
#NET "DDR3_DQ0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ1" LOC = R1;
#NET "DDR3_DQ1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ2" LOC = P2;
#NET "DDR3_DQ2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ3" LOC = P1;
#NET "DDR3_DQ3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ4" LOC = L3;
#NET "DDR3_DQ4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ5" LOC = L1;
#NET "DDR3_DQ5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ6" LOC = M2;
#NET "DDR3_DQ6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ7" LOC = M1;
#NET "DDR3_DQ7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ8" LOC = T2;
#NET "DDR3_DQ8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ9" LOC = T1;
#NET "DDR3_DQ9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ10" LOC = U3;
#NET "DDR3_DQ10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ11" LOC = U1;
#NET "DDR3_DQ11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ12" LOC = W3;
#NET "DDR3_DQ12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ13" LOC = W1;
#NET "DDR3_DQ13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ14" LOC = Y2;
#NET "DDR3_DQ14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ15" LOC = Y1;
#NET "DDR3_DQ15" IOSTANDARD = "LVCMOS15";
NET "fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fd_onewire_b" LOC = W11 ;
NET "fd_onewire_b" IOSTANDARD =LVCMOS25;
####################################################################################
# Misc
####################################################################################
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
# System clock
# DDR3
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
......@@ -566,9 +379,30 @@ TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fd_clk_ref_p_i" 8 ns HIGH 50%;
NET "clk_sys" TNM_NET = clk_sys;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys" TO "fd_clk_ref_p_i" TIG;
TIMESPEC ts_ignore_crossclock2 = FROM "fd_clk_ref_p_i" TO "clk_sys" TIG;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys" TO "fd_clk_ref_p_i" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_crossclock2 = FROM "fd_clk_ref_p_i" TO "clk_sys" 10ns DATAPATHONLY;
#bank 0
#PIN "U_GTP/gen2.refbufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "U_GTP/gen2.refbufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
#PIN "U_GTP/gen2.refbufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#gennum
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/04/26
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys" TO "clk_125m_pllref_n_i" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_sys" 10ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/04/26
TIMESPEC ts_x3 = FROM "clk_sys" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_sys" 10ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/04/27
TIMESPEC TS_x5 = FROM "U_DDR_PLL_clkout0" TO "clk_sys" 10ns DATAPATHONLY;
TIMESPEC TS_x6 = FROM "clk_sys" TO "U_DDR_PLL_clkout0" 10ns DATAPATHONLY;
hdl/top/spec/wr/spec_top.vhd
View file @ e8824c55
......@@ -6,63 +6,103 @@ use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wbconmax_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
generic
(
g_standalone : boolean := true;
g_debugging: boolean := false
g_simulation : integer := 0
);
port
(
-- Global ports
-------------------------------------------------------------------------
-- Standard SPEC ports (Gennum bridge, LEDS, Etc. Do not modify
-------------------------------------------------------------------------
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
-------------------------------------------------------------------------
-- PLL VCXO DAC Drive
-------------------------------------------------------------------------
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
--dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
fmc_scl_b : inout std_logic := '1';
fmc_sda_b : inout std_logic := '1';
carrier_onewire_b : inout std_logic := '1';
fmc_prsnt_m2c_l_i : in std_logic;
button1_i : in std_logic:='1';
button2_i : in std_logic:='1';
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
-- wr_ref_clk_p_i: in std_logic;
-- wr_ref_clk_n_i: in std_logic;
dbg_tbi_td_o: out std_logic_vector(9 downto 0);
dbg_tbi_rd_i: in std_logic_vector(9 downto 0) := "0000000000";
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic:='0';
sfp_rxn_i : in std_logic:='1';
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : inout std_logic; -- rate_select
sfp_mod_def0_b : in std_logic; -- detect pin
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
......@@ -71,19 +111,17 @@ entity spec_top is
-- Fine Delay Pins
-------------------------------------------------------------------------
fd_tdc_start_p_i : in std_logic := '0';
fd_tdc_start_n_i : in std_logic := '1';
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
fd_clk_ref_p_i : in std_logic := '0';
fd_clk_ref_n_i : in std_logic := '1';
fd_clk_ref_p_i : in std_logic;
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic := '1';
fd_trig_cal_o : out std_logic;
fd_trig_a_i : in std_logic;
fd_tdc_cal_pulse_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_a_o : out std_logic_vector(3 downto 0);
fd_tdc_emptyf_i : in std_logic := '1';
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_cs_n_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
......@@ -95,316 +133,39 @@ entity spec_top is
fd_spi_cs_gpio_n_o : out std_logic;
fd_spi_sclk_o : out std_logic;
fd_spi_mosi_o : out std_logic;
fd_spi_miso_i : in std_logic := '1';
fd_spi_miso_i : in std_logic;
fd_delay_len_o : out std_logic_vector(3 downto 0);
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd_dmtd_clk_o : out std_logic;
fd_dmtd_fb_in_i : in std_logic;
fd_dmtd_fb_out_i : in std_logic;
fd_pll_status_i : in std_logic;
fd_ext_rst_n_o : out std_logic;
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
onewire_b : inout std_logic;
fd_onewire_b : inout std_logic;
-----------------------------------------
--UART
-- UART
-----------------------------------------
uart_rxd_i : in std_logic:='1';
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
component wr_tbi_phy
port (
serdes_rst_i : in std_logic;
serdes_loopen_i : in std_logic;
serdes_prbsen_i : in std_logic;
serdes_enable_i : in std_logic;
serdes_syncen_i : in std_logic;
serdes_tx_data_i : in std_logic_vector(7 downto 0);
serdes_tx_k_i : in std_logic;
serdes_tx_disparity_o : out std_logic;
serdes_tx_enc_err_o : out std_logic;
serdes_rx_data_o : out std_logic_vector(7 downto 0);
serdes_rx_k_o : out std_logic;
serdes_rx_enc_err_o : out std_logic;
serdes_rx_bitslide_o : out std_logic_vector(3 downto 0);
tbi_refclk_i : in std_logic;
tbi_rbclk_i : in std_logic;
tbi_td_o : out std_logic_vector(9 downto 0);
tbi_rd_i : in std_logic_vector(9 downto 0);
tbi_syncen_o : out std_logic;
tbi_loopen_o : out std_logic;
tbi_prbsen_o : out std_logic;
tbi_enable_o : out std_logic);
end component;
component fine_delay_core
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
tm_time_valid_i : in std_logic := '0';
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tm_utc_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic := '0';
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_wr_i : in std_logic := '0';
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
generic(
-- g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26; -- DMA wishbone address bus width;
g_CSR_WB_MODE : string := "classic"
);
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-priv_log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
);
end component; -- gn4124_core
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFIO2
generic (
DIVIDE_BYPASS : boolean := true;
DIVIDE : integer := 1;
I_INVERT : boolean := false;
USE_DOUBLER : boolean := false);
port (
DIVCLK : out std_ulogic;
IOCLK : out std_ulogic;
SERDESSTROBE : out std_ulogic;
I : in std_ulogic);
end component;
component wr_core
generic (
g_simulation : integer;
g_virtual_uart : natural;
g_ep_rxbuf_size_log2 : integer;
g_dpram_initf : string;
g_dpram_size : integer;
g_num_gpio : integer);
port (
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic := '0';
rst_n_i : in std_logic;
pps_p_o : out std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
gpio_o : out std_logic_vector(g_num_gpio-1 downto 0);
gpio_i : in std_logic_vector(g_num_gpio-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_gpio-1 downto 0);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_addr_i : in std_logic_vector(c_aw-1 downto 0);
wb_data_i : in std_logic_vector(c_dw-1 downto 0);
wb_data_o : out std_logic_vector(c_dw-1 downto 0);
wb_sel_i : in std_logic_vector(c_sw-1 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
ext_snk_adr_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_dat_i : in std_logic_vector(15 downto 0) := x"0000";
ext_snk_sel_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_cyc_i : in std_logic := '0';
ext_snk_we_i : in std_logic := '0';
ext_snk_stb_i : in std_logic := '0';
ext_snk_ack_o : out std_logic;
ext_snk_err_o : out std_logic;
ext_snk_stall_o : out std_logic;
ext_src_adr_o : out std_logic_vector(1 downto 0);
ext_src_dat_o : out std_logic_vector(15 downto 0);
ext_src_sel_o : out std_logic_vector(1 downto 0);
ext_src_cyc_o : out std_logic;
ext_src_stb_o : out std_logic;
ext_src_we_o : out std_logic;
ext_src_ack_i : in std_logic := '1';
ext_src_err_i : in std_logic := '0';
ext_src_stall_i : in std_logic := '0';
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic := '0';
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic;
-- Timecode output
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
rst_aux_n_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0));
end component;
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_ch0_use_refclk_out : boolean := false;
g_ch1_use_refclk_out : boolean := false;
g_ch0_refclk_input : integer := 0;
g_ch1_refclk_input : integer := 0
);
g_simulation : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
......@@ -417,7 +178,6 @@ architecture rtl of spec_top is
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
......@@ -439,10 +199,91 @@ architecture rtl of spec_top is
pad_rxp1_i : in std_logic := '0');
end component;
component xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "wrc_stub.ram";
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
rst_aux_n_o : out std_logic
);
end component;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -456,83 +297,32 @@ architecture rtl of spec_top is
dac_din_o : out std_logic);
end component;
component chipscope_ila
component xmini_bone
generic (
g_class_mask : std_logic_vector(7 downto 0);
g_our_ethertype : std_logic_vector(15 downto 0));
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal s_TRIG0 : std_logic_vector(31 downto 0);
signal s_TRIG1 : std_logic_vector(31 downto 0);
signal s_TRIG2 : std_logic_vector(31 downto 0);
signal s_TRIG3 : std_logic_vector(31 downto 0);
component chipscope_icon
component fd_ddr_pll
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
signal rst : std_logic;
-- CSR wishbone bus
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal spi_wb_adr : std_logic_vector(4 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
signal irq_to_gn4124 : std_logic;
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
......@@ -541,24 +331,15 @@ architecture rtl of spec_top is
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
signal wrc_gpio_out : std_logic_vector(7 downto 0);
signal wrc_gpio_in : std_logic_vector(7 downto 0);
signal wrc_gpio_dir : std_logic_vector(7 downto 0);
signal wb_adr_wrc : std_logic_vector(17 downto 0);
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
......@@ -571,62 +352,49 @@ architecture rtl of spec_top is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
signal mbone_rst_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
signal local_reset_n : std_logic;
signal mbone_rst_n : std_logic;
signal mbone_src_out : t_wrf_source_out;
signal mbone_src_in : t_wrf_source_in;
signal mbone_snk_out : t_wrf_sink_out;
signal mbone_snk_in : t_wrf_sink_in;
signal mbone_wb_out : t_wishbone_master_out;
signal mbone_wb_in : t_wishbone_master_in;
component xmini_bone
generic (
g_class_mask : std_logic_vector(7 downto 0);
g_our_ethertype : std_logic_vector(15 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
constant c_NUM_WB_MASTERS : integer := 2;
constant c_NUM_WB_SLAVES : integer := 2;
constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_MINIBONE : integer := 1;
constant c_SLAVE_FD : integer := 0;
constant c_SLAVE_WRCORE : integer := 1;
signal mbone_wb_out : t_wishbone_master_out;
signal mbone_wb_in : t_wishbone_master_in;
signal host_wb_out : t_wishbone_master_out;
signal host_wb_in : t_wishbone_master_in;
signal dpram_slave2_in : t_wishbone_master_out;
constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(c_SLAVE_FD => x"00080000",
c_SLAVE_WRCORE => x"000c0000"
);
signal powerup_reset_reg : std_logic_vector(15 downto 0) := x"ffff";
constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(c_SLAVE_FD => x"000c0000",
c_SLAVE_WRCORE => x"000c0000"
);
signal cnx_out : t_wishbone_master_out_array(0 to 1);
signal cnx_in : t_wishbone_master_in_array(0 to 1);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in;
signal cnx_slave_out : t_wishbone_slave_out;
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal dcm_clk_ref_0, dcm_clk_ref_180 : std_logic;
signal fd_clk_ref : std_logic;
signal fd_tdc_start : std_logic;
signal onewire_en : std_logic;
signal scl_pad_out : std_logic;
signal scl_pad_in : std_logic;
signal scl_pad_oen : std_logic;
signal sda_pad_out : std_logic;
signal sda_pad_in : std_logic;
signal sda_pad_oen : std_logic;
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
......@@ -635,23 +403,110 @@ architecture rtl of spec_top is
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic;
signal wr_ref_clk_phyin : std_logic;
signal wr_ref_clk_phyout : std_logic;
signal ddr_pll_reset : std_logic;
signal ddr_pll_locked, fd_pll_status : std_logic;
signal fd_clk_ref_pin : std_logic;
signal fd_clk_ref_bufio_q : std_logic;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal fd_scl_out, fd_scl_in, fd_sda_out, fd_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal fd_owr_en, fd_owr_in : std_logic;
signal fd_irq : std_logic;
signal gn_wb_adr : std_logic_vector(31 downto 0);
signal pps : std_logic;
function f_int2bool (x : integer) return boolean is
begin
if(x = 0) then
return false;
else
return true;
end if;
end f_int2bool;
signal l_rst_n_synced : std_logic;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal dna_din : std_logic;
signal dna_dout : std_logic;
signal dna_clk : std_logic;
signal dna_shift : std_logic;
signal dna_read : std_logic;
begin
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_pllref,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
U_Sync_Reset : gc_sync_ffs
port map (
rst_n_i => '1',
data_i => L_RST_N,
synced_o => l_rst_n_synced,
clk_i => clk_sys);
process(clk_sys, L_RST_N)
begin
if L_RST_N = '0' then
local_reset_n <= '0';
elsif rising_edge(clk_sys) then
local_reset_n <= l_rst_n_synced;
end if;
end process;
U_Buf_CLK_PLL : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_Buf_CLK_GTP : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
cmp_sys_clk_pll : PLL_BASE
generic map (
......@@ -693,10 +548,10 @@ begin
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 62.5 MHz
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
......@@ -707,7 +562,7 @@ begin
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
......@@ -718,29 +573,6 @@ begin
CLKIN => clk_20m_vcxo_buf);
gen_standalone1 : if(g_standalone) generate
p_gen_reset : process(clk_sys)
begin
if rising_edge(clk_sys) then
button1_synced(0) <= button1_i;
button1_synced(1) <= button1_synced(0);
button1_synced(2) <= button1_synced(1);
if(powerup_reset_reg(15) /= '0')then
local_reset_n <= '0';
elsif (button1_synced(2) = '0') then
local_reset_n <= '0';
else
local_reset_n <= '1';
end if;
powerup_reset_reg <= powerup_reset_reg(14 downto 0) & '0';
end if;
end process;
end generate gen_standalone1;
cmp_clk_sys_buf : BUFG
port map (
......@@ -757,64 +589,146 @@ begin
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-------------------------------------------------------------------------------
-- Gennum core
-------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => fd_irq,
irq_p_o => GPIO(0),
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
dma_clk_i => clk_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_dat_i => (others => '0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0'
);
--cmp_l_clk_gtp : IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => wr_ref_clk_phyin,
-- I => wr_ref_clk_p_i,
-- IB => wr_ref_clk_n_i
-- );
--TRIG0 <= cnx_slave_in(c_MASTER_GENNUM).adr;
--TRIG1 <= cnx_slave_in(c_MASTER_GENNUM).dat;
--trig2(0) <= cnx_slave_in(c_MASTER_GENNUM).cyc;
--trig2(1) <= cnx_slave_in(c_MASTER_GENNUM).stb;
--trig2(3) <= cnx_slave_in(c_MASTER_GENNUM).we;
--trig2(4) <= cnx_slave_out(c_MASTER_GENNUM).ack;
--trig2(5) <= cnx_slave_out(c_MASTER_GENNUM).stall;
--trig2(6) <= cnx_master_out(c_SLAVE_WRCORE).cyc;
--trig2(7) <= cnx_master_out(c_SLAVE_WRCORE).stb;
--trig2(8) <= cnx_master_out(c_SLAVE_WRCORE).WE;
--trig2(9) <= cnx_master_in(c_SLAVE_WRCORE).ack;
--trig2(10) <= cnx_master_in(c_SLAVE_WRCORE).stall;
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-------------------------------------------------------------------------------
-- White Rabbit Core + PHY
-------------------------------------------------------------------------------
U_WR_CORE : wr_core
-- Tristates for FMC EEPROM
fmc_scl_b <= '0' when (wrc_scl_out = '0' or fd_scl_out = '0') else 'Z';
fmc_sda_b <= '0' when (wrc_sda_out = '0' or fd_sda_out = '0') else 'Z';
wrc_scl_in <= fmc_scl_b;
wrc_sda_in <= fmc_sda_b;
fd_scl_in <= fmc_scl_b;
fd_sda_in <= fmc_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
g_virtual_uart => 0,
g_ep_rxbuf_size_log2 => 12,
g_dpram_initf => "wrc_stub.ram",
g_dpram_size => 16384,
g_num_gpio => 8)
g_simulation => g_simulation,
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "",
g_dpram_size => 4096 * 5,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i => fd_clk_ref,
rst_n_i => local_reset_n,
pps_p_o => pps,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => dcm_clk_ref_0,
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
gpio_o => wrc_gpio_out,
gpio_i => wrc_gpio_in,
gpio_dir_o => wrc_gpio_dir,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wb_addr_i => cnx_out(0).adr(17 downto 0),
wb_data_i => cnx_out(0).dat,
wb_data_o => cnx_in(0).dat,
wb_sel_i => cnx_out(0).sel,
wb_we_i => cnx_out(0).we,
wb_cyc_i => cnx_out(0).cyc,
wb_stb_i => cnx_out(0).stb,
wb_ack_o => cnx_in(0).ack,
rst_aux_n_o => mbone_rst_n,
dio_o => open,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
......@@ -828,115 +742,68 @@ begin
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
tm_dac_wr_o => tm_dac_wr,
tm_dac_value_o => tm_dac_value,
tm_cycles_o => tm_cycles,
tm_utc_o => tm_utc,
tm_time_valid_o => tm_time_valid,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
led_red_o => LED_RED,
led_green_o => LED_GREEN,
ext_snk_adr_i => mbone_src_out.adr,
ext_snk_dat_i => mbone_src_out.dat,
ext_snk_sel_i => mbone_src_out.sel,
ext_snk_cyc_i => mbone_src_out.cyc,
ext_snk_we_i => mbone_src_out.we,
ext_snk_stb_i => mbone_src_out.stb,
ext_snk_ack_o => mbone_src_in.ack,
ext_snk_err_o => mbone_src_in.err,
ext_snk_stall_o => mbone_src_in.stall,
ext_src_adr_o => mbone_snk_in.adr,
ext_src_dat_o => mbone_snk_in.dat,
ext_src_sel_o => mbone_snk_in.sel,
ext_src_cyc_o => mbone_snk_in.cyc,
ext_src_stb_o => mbone_snk_in.stb,
ext_src_we_o => mbone_snk_in.we,
ext_src_ack_i => mbone_snk_out.ack,
ext_src_err_i => mbone_snk_out.err,
ext_src_stall_i => mbone_snk_out.stall
);
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_sys,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
--s_TRIG0(15 downto 0) <= mbone_snk_in.dat;
--s_TRIG0(17 downto 16) <= mbone_snk_in.adr;
--s_TRIG0(19 downto 18) <= mbone_snk_in.sel;
--s_TRIG0(20) <= mbone_snk_in.cyc;
--s_TRIG0(21) <= mbone_snk_in.stb;
--s_TRIG0(22) <= mbone_snk_in.we;
--s_TRIG0(23) <= mbone_snk_out.ack;
--s_TRIG0(24) <= mbone_snk_out.stall;
--s_TRIG1(15 downto 0) <= mbone_src_out.dat;
--s_TRIG1(17 downto 16) <= mbone_src_out.adr;
--s_TRIG1(19 downto 18) <= mbone_src_out.sel;
--s_TRIG1(20) <= mbone_src_out.cyc;
--s_TRIG1(21) <= mbone_src_out.stb;
--s_TRIG1(22) <= mbone_src_out.we;
--s_TRIG1(23) <= mbone_src_in.ack;
--s_TRIG1(24) <= mbone_src_in.stall;
--s_trig1(25) <= mbone_wb_out.cyc;
--s_trig1(26) <= mbone_wb_out.stb;
--s_trig1(27) <= mbone_wb_out.we;
--s_trig1(28) <= mbone_wb_in.ack;
--s_trig1(29) <= cnx_out(0).cyc;
--s_trig1(30) <= cnx_out(0).stb;
--s_trig1(31) <= cnx_out(0).we;
--s_trig0(28) <= cnx_in(0).ack;
--s_trig2 <= mbone_wb_out.dat;
--s_trig3 <= mbone_wb_out.adr;
wrf_src_o => mbone_snk_in,
wrf_src_i => mbone_snk_out,
wrf_snk_o => mbone_src_in,
wrf_snk_i => mbone_src_out,
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_utc_o => tm_utc,
tm_cycles_o => tm_cycles,
--process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- trig0 <= s_trig0;
-- trig1 <= s_trig1;
-- trig2 <= s_trig2;
-- trig3 <= s_trig3;
-- end if;
--end process;
rst_aux_n_o => mbone_rst_n,
pps_p_o => pps
);
U_MiniBone : xmini_bone
U_Intercon : xwb_crossbar
generic map (
g_class_mask => x"f0",
g_our_ethertype => x"a0a0")
g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => c_cnx_base_addr,
g_mask => c_cnx_base_mask)
port map (
clk_sys_i => clk_sys,
rst_n_i => mbone_rst_n,
src_o => mbone_src_out,
src_i => mbone_src_in,
snk_o => mbone_snk_out,
snk_i => mbone_snk_in,
master_o => mbone_wb_out,
master_i => mbone_wb_in);
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
-- gen_real_phy: if(g_debugging = false) generate
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => 0,
g_ch1_use_refclk_out => false,
g_ch0_use_refclk_out => false)
g_simulation => g_simulation)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_ref_clk_o => open,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
......@@ -950,7 +817,6 @@ begin
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_ref_clk_o => open,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
......@@ -961,7 +827,7 @@ begin
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_loopen_i => '0', --phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
......@@ -970,32 +836,35 @@ begin
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
-- end generate gen_real_phy;
gen_debug_phy: if(g_debugging = true) generate
U_Debug: wr_tbi_phy
port map (
serdes_rst_i => phy_rst,
serdes_loopen_i => phy_loopen,
serdes_prbsen_i => '0',
serdes_enable_i => '1',
serdes_syncen_i => '1',
serdes_tx_data_i => phy_tx_data,
serdes_tx_k_i => phy_tx_k,
serdes_tx_disparity_o => phy_tx_disparity,
serdes_tx_enc_err_o => phy_tx_enc_err,
serdes_rx_data_o => phy_rx_data,
serdes_rx_k_o => phy_rx_k,
serdes_rx_enc_err_o => phy_rx_enc_err,
serdes_rx_bitslide_o => phy_rx_bitslide,
tbi_refclk_i => clk_125m_pllref,
tbi_rbclk_i => phy_rx_rbclk,
tbi_td_o => dbg_tbi_td_o,
tbi_rd_i => dbg_tbi_rd_i);
phy_rx_rbclk <= clk_125m_pllref;
end generate gen_debug_phy;
trig0(7 downto 0) <= phy_tx_data;
trig0(8) <= phy_tx_k;
trig0(9) <= phy_tx_disparity;
trig0(10) <= phy_tx_enc_err;
trig1(7 downto 0) <= phy_rx_data;
trig1(8) <= phy_rx_k;
trig1(10) <= phy_rx_enc_err;
trig1(11) <= phy_rst;
trig1(15 downto 12) <= phy_rx_bitslide;
U_MiniBone : xmini_bone
generic map (
g_class_mask => x"f0",
g_our_ethertype => x"a0a0")
port map (
clk_sys_i => clk_sys,
rst_n_i => mbone_rst_n,
src_o => mbone_src_out,
src_i => mbone_src_in,
snk_o => mbone_snk_out,
snk_i => mbone_snk_in,
master_o => mbone_wb_out,
master_i => mbone_wb_in);
cnx_slave_in(c_MASTER_MINIBONE).cyc <= '0';
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
......@@ -1013,24 +882,11 @@ begin
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
dac_clr_n_o => open,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_125m_pllref,
rst_n_i => local_reset_n,
pulse_i => pps,
extended_o => LED_RED);
LED_GREEN <= wrc_gpio_out(0);
sfp_mod_def0_b <= '0';
sfp_mod_def1_b <= '0';
sfp_mod_def2_b <= '0';
-- dac_clr_n_o <= '1';
sfp_tx_disable_o <= '0';
......@@ -1038,133 +894,6 @@ begin
-- FINE DELAY INSTANTIATION
-------------------------------------------------------------------------------
U_Fanout : xwb_bus_fanout
generic map (
g_num_outputs => 2,
g_bits_per_slave => 18)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => mbone_wb_out,
slave_o => mbone_wb_in,
master_i => cnx_in,
master_o => cnx_out);
-- cnx_in(1).ack <= '0';
U_DELAY_CORE : fine_delay_core
port map (
clk_ref_i => fd_clk_ref,
tdc_start_i => fd_tdc_start,
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
trig_a_n_i => fd_trig_a_i,
trig_cal_o => fd_trig_cal_o,
led_trig_o => fd_led_trig_o,
acam_a_o => fd_tdc_a_o,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_err_i => '0',
acam_int_i => '0',
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_cs_n_o => fd_tdc_cs_n_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr,
tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid,
tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
i2c_scl_i => fmc_scl_b,
i2c_scl_o => scl_pad_out,
i2c_scl_oen_o => scl_pad_oen,
i2c_sda_i => fmc_sda_b,
i2c_sda_o => sda_pad_out,
i2c_sda_oen_o => sda_pad_oen,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
owr_i => onewire_b,
owr_en_o => onewire_en,
wb_adr_i => cnx_out(1).adr(7 downto 0),
wb_dat_i => cnx_out(1).dat,
wb_dat_o => cnx_in(1).dat,
wb_cyc_i => cnx_out(1).cyc,
wb_stb_i => cnx_out(1).stb,
wb_we_i => cnx_out(1).we,
wb_ack_o => cnx_in(1).ack);
cmp_fd_refclk : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => fd_clk_ref, -- Buffer output
I => fd_clk_ref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_clk_ref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
--U_FD_CLK_wtfbuf1: BUFIO2
-- port map (
-- DIVCLK => fd_clk_ref_bufio_q,
-- IOCLK => open,
-- SERDESSTROBE => open,
-- I => fd_clk_ref_pin);
--U_FD_CLK_wtfbuf2: BUFG
-- port map (
-- I => fd_clk_ref_bufio_q,
-- O => fd_clk_ref
-- );
process(clk_sys)
begin
if rising_edge(clk_sys) then
wrc_gpio_in(1) <= dna_dout;
dna_din <= wrc_gpio_out(1);
dna_read <= wrc_gpio_out(2);
dna_shift <= wrc_gpio_out(3);
dna_clk <= wrc_gpio_out(4);
end if;
end process;
U_DNA: DNA_PORT
port map (
DOUT => dna_dout,
CLK => dna_clk,
DIN => dna_din,
READ => dna_read,
SHIFT => dna_shift);
cmp_pll_refclk : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i
);
cmp_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
......@@ -1176,19 +905,101 @@ process(clk_sys)
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= fmc_scl_b;
sda_pad_in <= fmc_sda_b;
U_DDR_PLL : fd_ddr_pll
port map (
RST => ddr_pll_reset,
LOCKED => ddr_pll_locked,
CLK_IN1_P => fd_clk_ref_p_i,
CLK_IN1_N => fd_clk_ref_n_i,
CLK_OUT1 => dcm_clk_ref_0,
CLK_OUT2 => dcm_clk_ref_180);
ddr_pll_reset <= not fd_pll_status_i;
fd_pll_status <= fd_pll_status_i and ddr_pll_locked;
U_FineDelay_Core : fine_delay_core
generic map (
g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => dcm_clk_ref_0,
clk_ref_180_i => dcm_clk_ref_180,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
rst_n_i => local_reset_n,
dcm_reset_o => open,
dcm_locked_i => ddr_pll_locked,
trig_a_i => fd_trig_a_i,
tdc_cal_pulse_o => fd_tdc_cal_pulse_o,
tdc_start_i => fd_tdc_start,
dmtd_fb_in_i => fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd_dmtd_fb_out_i,
dmtd_samp_o => fd_dmtd_clk_o,
led_trig_o => fd_led_trig_o,
ext_rst_n_o => fd_ext_rst_n_o,
pll_status_i => fd_pll_status,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr,
owr_en_o => fd_owr_en,
owr_i => fd_owr_in,
i2c_scl_oen_o => fd_scl_out,
i2c_scl_i => fd_scl_in,
i2c_sda_oen_o => fd_sda_out,
i2c_sda_i => fd_sda_in,
fmc_present_n_i => fmc_prsnt_m2c_l_i,
wb_adr_i => cnx_master_out(c_SLAVE_FD).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD).stall,
wb_irq_o => fd_irq);
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
onewire_b <= '0' when onewire_en = '0' else 'Z';
fd_onewire_b <= '0' when fd_owr_en = '1' else 'Z';
fd_owr_in <= fd_onewire_b;
end rtl;
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