doc/design-notes: fixes after Erik's feedback

e8cf7876 · Tomasz Wlostowski · dc61674f · e8cf7876 · e8cf7876 · e8cf7876
Commit e8cf7876 authored Jul 09, 2013 by Tomasz Wlostowski
13 changed files
--- a/doc/design-notes/Makefile
+++ b/doc/design-notes/Makefile
@@ -6,7 +6,7 @@
 #################

 # There is not basenames here, all *.in are considered input
-INPUT = fine-delay.in
+INPUT = fine-delay-design-notes.in

 TEXI = $(INPUT:.in=.texi)
 INFO = $(INPUT:.in=.info)

--- a/doc/design-notes/drawings/block_diagram.cdr
+++ b/doc/design-notes/drawings/block_diagram.cdr
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--- a/doc/design-notes/drawings/block_diagram.pdf
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--- a/doc/design-notes/drawings/vhdl_output_stage.pdf
+++ b/doc/design-notes/drawings/vhdl_output_stage.pdf
--- a/doc/design-notes/fd_channel_regs.in
+++ b/doc/design-notes/fd_channel_regs.in
+@regsection Memory map summary
+@multitable  @columnfractions .10 .15 .15 .55
+@headitem Address @tab Type @tab Prefix @tab Name
+@item @code{0x0} @tab
+REG @tab
+@code{DCR} @tab
+Delay Control Register
+@item @code{0x4} @tab
+REG @tab
+@code{FRR} @tab
+Fine Range Register
+@item @code{0x8} @tab
+REG @tab
+@code{U_STARTH} @tab
+Pulse start time / offset (MSB TAI seconds)
+@item @code{0xc} @tab
+REG @tab
+@code{U_STARTL} @tab
+Pulse start time / offset (LSB TAI seconds)
+@item @code{0x10} @tab
+REG @tab
+@code{C_START} @tab
+Pulse start time / offset (8 ns cycles)
+@item @code{0x14} @tab
+REG @tab
+@code{F_START} @tab
+Pulse start time / offset (fine part)
+@item @code{0x18} @tab
+REG @tab
+@code{U_ENDH} @tab
+Pulse end time / offset (MSB TAI seconds)
+@item @code{0x1c} @tab
+REG @tab
+@code{U_ENDL} @tab
+Pulse end time / offset (LSB TAI seconds)
+@item @code{0x20} @tab
+REG @tab
+@code{C_END} @tab
+Pulse end time / offset (8 ns cycles)
+@item @code{0x24} @tab
+REG @tab
+@code{F_END} @tab
+Pulse end time / offset (fine part)
+@item @code{0x28} @tab
+REG @tab
+@code{U_DELTA} @tab
+Pulse spacing (TAI seconds)
+@item @code{0x2c} @tab
+REG @tab
+@code{C_DELTA} @tab
+Pulse spacing (8 ns cycles)
+@item @code{0x30} @tab
+REG @tab
+@code{F_DELTA} @tab
+Pulse spacing (fine part)
+@item @code{0x34} @tab
+REG @tab
+@code{RCR} @tab
+Repeat Count Register
+@end multitable 
+@regsection @code{DCR} - Delay Control Register
+Main control registers of the particular output channel of the Fine Delay Core.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/W @tab
+@code{ENABLE}
+@tab @code{0} @tab 
+Enable channel
+@item @code{1}
+@tab R/W @tab
+@code{MODE}
+@tab @code{0} @tab 
+Delay mode select
+@item @code{2}
+@tab W/O @tab
+@code{PG_ARM}
+@tab @code{0} @tab 
+Pulse generator arm
+@item @code{3}
+@tab R/O @tab
+@code{PG_TRIG}
+@tab @code{X} @tab 
+Pulse generator triggered
+@item @code{4}
+@tab W/O @tab
+@code{UPDATE}
+@tab @code{0} @tab 
+Update delay/absolute trigger time
+@item @code{5}
+@tab R/O @tab
+@code{UPD_DONE}
+@tab @code{X} @tab 
+Delay update done flag
+@item @code{6}
+@tab W/O @tab
+@code{FORCE_DLY}
+@tab @code{0} @tab 
+Force calibration delay
+@item @code{7}
+@tab R/W @tab
+@code{NO_FINE}
+@tab @code{0} @tab 
+Disable fine part update
+@item @code{8}
+@tab R/W @tab
+@code{FORCE_HI}
+@tab @code{0} @tab 
+Force output high
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{ENABLE} @tab write 0: channel is disabled. Output is driven LOW.@* write 1: channel is enabled. Output may produce pulses.
+@item @code{MODE} @tab 0: Channel will work as a delay generator, producing delayed copies of pulses coming to the trigger input. Start/End registers shall contain delays of respectively, the rising and falling edge.@* 1: Channel will work as a programmable pulse generator - producing a pulse which begins and ends at absolute TAI times stored in Start/End registers.@* @b{Note:} @code{MODE} bit can be safely set only when the delay logic is disabled (i.e. when @code{DCR.ENABLE == 0})
+@item @code{PG_ARM} @tab write 1: arms the pulse generator. @* write 0: no effect.@* @b{Note:} The values written to @code{[U/C/F]_START} and @code{[U/C/F]_END} must be bigger by at least 300 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much higher, as it's affected by the non-determinism of the operating system.
+@item @code{PG_TRIG} @tab read 1: pulse generator has been triggered and produced a pulse@* read 0: pulse generator is busy or hasn't triggered yet
+@item @code{UPDATE} @tab write 1: Starts the update procedure. The start and end times from @code{[U/C/F][START/END]} will be transferred in an atomic way to the internal delay/pulse generator registers.@* write 0: no effect.@* @b{Note:} Care must be taken when updating the delay value - if the channel gets stuck due to invalid control values written, the only way to bring it back alive is to disable and re-enable it by toggling @code{DCR.ENABLE} bit.
+@item @code{UPD_DONE} @tab read 1: the delays from @code{[U/C/F][START/END]} have been loaded into internal registers. Subsequent triggers will be delayed by the newly programmed value.@* read 0: update operation in progress
+@item @code{FORCE_DLY} @tab Used in type 1 calibration.@* write 1: preloads the SY89295 delay line with the contents of FRR register.@* write 0: no effect
+@item @code{NO_FINE} @tab write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ns). @*write 0: normal operation. Pulse width/spacing must be at least 200 ns, width/spacing resolution is 10 ps.@*@b{Note:} A typical use case for @code{NO_FINE} bit is producing a 10 MHz clock.
+@item @code{FORCE_HI} @tab write 1: forces constant 1 on the output when the channel is disabled@* write 0: forces constant 0 on the output when the channel is disabled@* Used for testing/calibration purposes.
+@end multitable
+@regsection @code{FRR} - Fine Range Register
+Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0. Used by type 1 calibration logic.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{9...0}
+@tab R/W @tab
+@code{FRR}
+@tab @code{0} @tab 
+Fine range in SY89825 taps.
+@end multitable
+@regsection @code{U_STARTH} - Pulse start time / offset (MSB TAI seconds)
+TAI seconds (8 upper bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/W @tab
+@code{U_STARTH}
+@tab @code{0} @tab 
+TAI seconds (MSB)
+@end multitable
+@regsection @code{U_STARTL} - Pulse start time / offset (LSB TAI seconds)
+TAI seconds (32 lower bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/W @tab
+@code{U_STARTL}
+@tab @code{0} @tab 
+TAI seconds (LSB)
+@end multitable
+@regsection @code{C_START} - Pulse start time / offset (8 ns cycles)
+Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{C_START}
+@tab @code{0} @tab 
+Reference clock cycles
+@end multitable
+@regsection @code{F_START} - Pulse start time / offset (fine part)
+Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{11...0}
+@tab R/W @tab
+@code{F_START}
+@tab @code{0} @tab 
+Fractional part
+@end multitable
+@regsection @code{U_ENDH} - Pulse end time / offset (MSB TAI seconds)
+TAI seconds (8 upper bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/W @tab
+@code{U_ENDH}
+@tab @code{0} @tab 
+TAI seconds (MSB)
+@end multitable
+@regsection @code{U_ENDL} - Pulse end time / offset (LSB TAI seconds)
+TAI seconds (32 lower bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/W @tab
+@code{U_ENDL}
+@tab @code{0} @tab 
+TAI seconds (LSB)
+@end multitable
+@regsection @code{C_END} - Pulse end time / offset (8 ns cycles)
+Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{C_END}
+@tab @code{0} @tab 
+Reference clock cycles
+@end multitable
+@regsection @code{F_END} - Pulse end time / offset (fine part)
+Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). 
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{11...0}
+@tab R/W @tab
+@code{F_END}
+@tab @code{0} @tab 
+Fractional part
+@end multitable
+@regsection @code{U_DELTA} - Pulse spacing (TAI seconds)
+TAI seconds between the rising edges of subsequent output pulses.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{3...0}
+@tab R/W @tab
+@code{U_DELTA}
+@tab @code{0} @tab 
+TAI seconds
+@end multitable
+@regsection @code{C_DELTA} - Pulse spacing (8 ns cycles)
+Reference clock cycles between the rising edges of subsequent output pulses.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{C_DELTA}
+@tab @code{0} @tab 
+Reference clock cycles
+@end multitable
+@regsection @code{F_DELTA} - Pulse spacing (fine part)
+Sub-cycle part of spacing between the rising edges of subsequent output pulses.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{11...0}
+@tab R/W @tab
+@code{F_DELTA}
+@tab @code{0} @tab 
+Fractional part
+@end multitable
+@regsection @code{RCR} - Repeat Count Register
+Register controlling the number of output pulses to be generated upon reception of a trigger pulse or triggering the channel in PG mode.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{15...0}
+@tab R/W @tab
+@code{REP_CNT}
+@tab @code{0} @tab 
+Repeat Count
+@item @code{16}
+@tab R/W @tab
+@code{CONT}
+@tab @code{0} @tab 
+Continuous Waveform Mode
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{REP_CNT} @tab Equal to desired number of pulses minus 1 (0 = 1 pulse, 0xffff = 65536 pulses)
+@item @code{CONT} @tab write 1: output will produce a contiguous square wave upon reception of trigger pulse. The generation can be aborted only disabling the channel (clearing @code{DCR.ENABLE})@* write 0: each trigger will produce @code{RCR.REP_CNT+1} pulses.
+@end multitable
--- a/doc/design-notes/fd_main_regs.in
+++ b/doc/design-notes/fd_main_regs.in
+@regsection Memory map summary
+@multitable  @columnfractions .08 .08 .15 .64
+@headitem Address @tab Type @tab Prefix @tab Name
+@item @code{0x0} @tab
+REG @tab
+@code{RSTR} @tab
+Reset Register
+@item @code{0x4} @tab
+REG @tab
+@code{IDR} @tab
+ID Register
+@item @code{0x8} @tab
+REG @tab
+@code{GCR} @tab
+Global Control Register
+@item @code{0xc} @tab
+REG @tab
+@code{TCR} @tab
+Timing Control Register
+@item @code{0x10} @tab
+REG @tab
+@code{TM_SECH} @tab
+Time Register - TAI seconds (MSB)
+@item @code{0x14} @tab
+REG @tab
+@code{TM_SECL} @tab
+Time Register - TAI seconds (LSB)
+@item @code{0x18} @tab
+REG @tab
+@code{TM_CYCLES} @tab
+Time Register - sub-second 125 MHz clock cycles 
+@item @code{0x1c} @tab
+REG @tab
+@code{TDR} @tab
+Host-driven TDC Data Register.
+@item @code{0x20} @tab
+REG @tab
+@code{TDCSR} @tab
+Host-driven TDC Control/Status
+@item @code{0x24} @tab
+REG @tab
+@code{CALR} @tab
+Calibration register
+@item @code{0x28} @tab
+REG @tab
+@code{DMTR_IN} @tab
+DMTD Input Tag Register
+@item @code{0x2c} @tab
+REG @tab
+@code{DMTR_OUT} @tab
+DMTD Output Tag Register
+@item @code{0x30} @tab
+REG @tab
+@code{ADSFR} @tab
+Acam Scaling Factor Register
+@item @code{0x34} @tab
+REG @tab
+@code{ATMCR} @tab
+Acam Timestamp Merging Control Register
+@item @code{0x38} @tab
+REG @tab
+@code{ASOR} @tab
+Acam Start Offset Register
+@item @code{0x3c} @tab
+REG @tab
+@code{IECRAW} @tab
+Raw Input Events Counter Register
+@item @code{0x40} @tab
+REG @tab
+@code{IECTAG} @tab
+Tagged Input Events Counter Register
+@item @code{0x44} @tab
+REG @tab
+@code{IEPD} @tab
+Input Event Processing Delay Register
+@item @code{0x48} @tab
+REG @tab
+@code{SCR} @tab
+SPI Control Register
+@item @code{0x4c} @tab
+REG @tab
+@code{RCRR} @tab
+Reference Clock Rate Register
+@item @code{0x50} @tab
+REG @tab
+@code{TSBCR} @tab
+Timestamp Buffer Control Register
+@item @code{0x54} @tab
+REG @tab
+@code{TSBIR} @tab
+Timestamp Buffer Interrupt Register
+@item @code{0x58} @tab
+REG @tab
+@code{TSBR_SECH} @tab
+Timestamp Buffer Readout Seconds Register (MSB)
+@item @code{0x5c} @tab
+REG @tab
+@code{TSBR_SECL} @tab
+Timestamp Buffer Readout Seconds Register (LSB)
+@item @code{0x60} @tab
+REG @tab
+@code{TSBR_CYCLES} @tab
+Timestamp Buffer Readout Cycles Register
+@item @code{0x64} @tab
+REG @tab
+@code{TSBR_FID} @tab
+Timestamp Buffer Readout Fine/Channel/Sequence ID Register
+@item @code{0x68} @tab
+REG @tab
+@code{I2CR} @tab
+I2C Bit-banged IO Register
+@item @code{0x6c} @tab
+REG @tab
+@code{TDER1} @tab
+Test/Debug Register 1
+@item @code{0x70} @tab
+REG @tab
+@code{TDER2} @tab
+Test/Debug Register 1
+@item @code{0x74} @tab
+REG @tab
+@code{TSBR_DEBUG} @tab
+Timestamp Buffer Debug Values Register
+@item @code{0x78} @tab
+REG @tab
+@code{TSBR_ADVANCE} @tab
+Timestamp Buffer Advance Register
+@item @code{0x80} @tab
+REG @tab
+@code{EIC_IDR} @tab
+Interrupt disable register
+@item @code{0x84} @tab
+REG @tab
+@code{EIC_IER} @tab
+Interrupt enable register
+@item @code{0x88} @tab
+REG @tab
+@code{EIC_IMR} @tab
+Interrupt mask register
+@item @code{0x8c} @tab
+REG @tab
+@code{EIC_ISR} @tab
+Interrupt status register
+@end multitable 
+@regsection @code{RSTR} - Reset Register
+Controls software reset of the Fine Delay core and the mezzanine connected to it. Both reset lines are driven indepentently, there is also an unlock word provided to prevent resetting the board/core by accidentally accessing this register.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{RST_FMC}
+@tab @code{0} @tab 
+State of the reset Line of the Mezzanine (EXT_RST_N pin)
+@item @code{1}
+@tab W/O @tab
+@code{RST_CORE}
+@tab @code{0} @tab 
+State of the reset of the Fine Delay Core
+@item @code{31...16}
+@tab W/O @tab
+@code{LOCK}
+@tab @code{0} @tab 
+Reset magic value
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{RST_FMC} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation
+@item @code{RST_CORE} @tab write 0: FD Core is held in reset@* write 1: Normal FD Core operation
+@item @code{LOCK} @tab Protection field - the state of FMC and core lines will@* only be updated if @code{LOCK} is written with 0xdead together with the new state of the reset lines.
+@end multitable
+@regsection @code{IDR} - ID Register
+Magic identification value (for detecting FD cores by the driver). Even though now enumeration is handled through SDB, the @code{IDR} register is kept for compatibility with older software.
+@multitable @columnfractions .10 .10 .15 .30 .35
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{IDR}
+@tab @code{0xf19ede1a} @tab 
+ID Magic Value
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{IDR} @tab Equal to @code{0xf19ede1a}
+@end multitable
+@regsection @code{GCR} - Global Control Register
+Common control bits used throughout the core.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/W @tab
+@code{BYPASS}
+@tab @code{0} @tab 
+Bypass hardware TDC controller
+@item @code{1}
+@tab R/W @tab
+@code{INPUT_EN}
+@tab @code{0} @tab 
+Enable trigger input
+@item @code{2}
+@tab R/O @tab
+@code{DDR_LOCKED}
+@tab @code{X} @tab 
+PLL lock status
+@item @code{3}
+@tab R/O @tab
+@code{FMC_PRESENT}
+@tab @code{X} @tab 
+Mezzanine present
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{BYPASS} @tab Descides who is in charge of the TDC and delay lines:@* write 0: TDC and delay lines are controlled by the HDL core (normal operation mode)@* write 1: TDC and delay lines controlled from the host via @code{TDR} and @code{TDCSR} registers (calibration and testing mode)
+@item @code{INPUT_EN} @tab write 1: trigger input is enabled@* write 0: trigger input is disabled@* @b{Note 1:} state of @code{INPUT_EN} is relevant only in normal operation mode (i.e. when @code{GCR.BYPASS} == 0). @* @b{Note 2:} enabling the input in @code{INPUT_EN} does not mean it will be automatically enabled in the ACAM TDC - one must pre-program its registers first.
+@item @code{DDR_LOCKED} @tab read 1: AD9516 and internal DDR PLLs are locked@* read 0: AD9516 or internal DDR PLL not (yet) locked
+@item @code{FMC_PRESENT} @tab Mirrors the state of the FMC's @code{PRSNT_L} hardware pin: @* read 1: FMC card is present (@code{PRSNT_L == 0})@* read 0: no FMC card in the slot (@code{PRSNT_L == 1})
+@end multitable
+@regsection @code{TCR} - Timing Control Register
+Controls time setting and White Rabbit/local time base selection.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/O @tab
+@code{DMTD_STAT}
+@tab @code{X} @tab 
+DMTD Clock Status
+@item @code{1}
+@tab R/W @tab
+@code{WR_ENABLE}
+@tab @code{0} @tab 
+WR Timing Enable
+@item @code{2}
+@tab R/O @tab
+@code{WR_LOCKED}
+@tab @code{X} @tab 
+WR Timing Locked
+@item @code{3}
+@tab R/O @tab
+@code{WR_PRESENT}
+@tab @code{X} @tab 
+WR Core Present
+@item @code{4}
+@tab R/O @tab
+@code{WR_READY}
+@tab @code{X} @tab 
+WR Core Time Ready
+@item @code{5}
+@tab R/O @tab
+@code{WR_LINK}
+@tab @code{X} @tab 
+WR Core Link Up
+@item @code{6}
+@tab W/O @tab
+@code{CAP_TIME}
+@tab @code{0} @tab 
+Capture Current Time
+@item @code{7}
+@tab W/O @tab
+@code{SET_TIME}
+@tab @code{0} @tab 
+Set Current Time
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{DMTD_STAT} @tab Status of the DMTD (helper) clock, used for DDMTD calibration purposes by the test suite.@* read 0: DMTD clock is not available or has been lost since last read operation of @code{TCR} register@* read 1: DMTD clock has been OK since previous read of @code{TCR} register
+@item @code{WR_ENABLE} @tab Enables/disables WR synchronization.@* write 1: WR synchronization is enabled. Poll the @code{TCR.WR_LOCKED} bit to check if the WR Core is still locked.@* write 0: WR synchronization is disabled, the card is in free running mode.@* @b{Note:} enabling WR synchronization will cause a jump in the time base counter of the core. This may lead to lost pulses, therefore it is strongly recommended do disable the inputs/outputs before entering WR mode. When WR mode is disabled, the core will continue counting without a jump.
+@item @code{WR_LOCKED} @tab Status of WR synchronization. @* read 0: local oscillator/time base is not locked to WR (or a transient delock event occured since last read of @code{TCR} register).@* read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time. 
+@item @code{WR_PRESENT} @tab Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state of the @code{g_with_wr_core} generic HDL parameter. @* read 0: No WR Core present. Enabling WR will have no effect.@* read 1: WR Core available.
+@item @code{WR_READY} @tab Indicates the status of synchronization of the associated WR core. Valid only if @code{TCR.WR_PRESENT} bit is set.@* read 0: WR Core is not synchronzied yet: there is no link, no PTP master in the network or synchronization is in progress.@* read 1: WR Core time is ready. User may enable WR reference by setting @code{TCR.WR_ENABLE} bit.@* @b{Note:} it is allowed to enable the WR mode even if @code{TCR.WR_READY} or @code{TCR.WR_LINK} bits are not set. Time base will be synced to WR as soon as the core gets correct PTP time from the master.
+@item @code{WR_LINK} @tab Reflects the state of the WR Core's Ethernet link. Provided as an additional diagnostic feature.@* read 0: Ethernet link is down.@* read 1: Ethernet link is up.
+@item @code{CAP_TIME} @tab Performs an atomic read of the core's current time.@* write 1: transfers the current value of seconds/cycles counters to @code{TM_} registers.@* write 0: no effect.
+@item @code{SET_TIME} @tab Sets internal time base counter to a given time in an atomic way:@* write 1: transfers the current value of @code{TM_} registers to the timebase counter.@* write 0: no effect.@* @b{Note 1:} Internal time counters must be always initialized to a known value (e.g. zeroes), after every reset/power cycle.@* @b{Note 2:} Writing to @code{TCR.SET_TIME} while WR mode is active is forbidden. If you do so, prepare for unforeseen consequences.
+@end multitable
+@regsection @code{TM_SECH} - Time Register - TAI seconds (MSB)
+Seconds counter, most significant part@* read: value of internal seconds counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of seconds counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/W @tab
+@code{TM_SECH}
+@tab @code{X} @tab 
+TAI seconds (MSB)
+@end multitable
+@regsection @code{TM_SECL} - Time Register - TAI seconds (LSB)
+Seconds counter, least significant part@* read: value of internal seconds counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of seconds counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/W @tab
+@code{TM_SECL}
+@tab @code{X} @tab 
+TAI seconds (LSB)
+@end multitable
+@regsection @code{TM_CYCLES} - Time Register - sub-second 125 MHz clock cycles 
+Number of 125 MHz reference clock cycles from the beginning of the current second. @* read: value of cycles counter taken upon last write to @code{TCR.CAP_TIME} bit.@* write: new value of cycles counter (loaded to the time base counter by writing @code{TCR.SET_TIME} bit)
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{TM_CYCLES}
+@tab @code{X} @tab 
+Reference clock cycles (0...124999999)
+@end multitable
+@regsection @code{TDR} - Host-driven TDC Data Register.
+Holds the 28-bit data word read from/to be written to the ACAM TDC, when the core is configured in bypass mode (@code{GCR.BYPASS == 1}).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{TDR}
+@tab @code{X} @tab 
+TDC Data
+@end multitable
+@regsection @code{TDCSR} - Host-driven TDC Control/Status
+Allows controlling the TDC directly from the host (when @code{GCR.BYPASS == 1}).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{WRITE}
+@tab @code{0} @tab 
+Write to TDC
+@item @code{1}
+@tab W/O @tab
+@code{READ}
+@tab @code{0} @tab 
+Read from TDC
+@item @code{2}
+@tab R/O @tab
+@code{EMPTY}
+@tab @code{X} @tab 
+Empty flag
+@item @code{3}
+@tab W/O @tab
+@code{STOP_EN}
+@tab @code{0} @tab 
+Stop enable
+@item @code{4}
+@tab W/O @tab
+@code{START_DIS}
+@tab @code{0} @tab 
+Start disable
+@item @code{5}
+@tab W/O @tab
+@code{START_EN}
+@tab @code{0} @tab 
+Start enable
+@item @code{6}
+@tab W/O @tab
+@code{STOP_DIS}
+@tab @code{0} @tab 
+Stop disable
+@item @code{7}
+@tab W/O @tab
+@code{ALUTRIG}
+@tab @code{0} @tab 
+Pulse <code>Alutrigger</code> line
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{WRITE} @tab Writes the data word from @code{TDR} register to the ACAM TDC.@* write 1: write the data word programmed in @code{TDR} register to the TDC. The TDC address must be set via the SPI I/O expander.@* write 0: no effect.
+@item @code{READ} @tab Reads a data word from the TDC and puts it in @code{TDR} register.@* write 1: read a data word from the TDC. The read word will be put in @code{TDR} register. The TDC address must be set via the SPI I/O expander.@* write 0: no effect.
+@item @code{EMPTY} @tab Raw status of the @code{EF} (FIFO empty) pin of the TDC.@* read 0: there is one (or more) pending timestamp(s) in the ACAM's internal FIFO.@* read 1: the internal TDC FIFO is empty (no timestamps to read).
+@item @code{STOP_EN} @tab Controls the @code{StopDis} input of the TDC.@* write 1: enables the TDC stop input.@* write 0: no effect.
+@item @code{START_DIS} @tab Controls the @code{StartDis} input of the TDC.@* write 1: disables the TDC start input.@* write 0: no effect.
+@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
+@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
+@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
+@end multitable
+@regsection @code{CALR} - Calibration register
+Controls calibration logic.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{CAL_PULSE}
+@tab @code{0} @tab 
+Generate calibration pulses (type 1 calibration)
+@item @code{1}
+@tab R/W @tab
+@code{CAL_PPS}
+@tab @code{0} @tab 
+PPS calibration output enable.
+@item @code{2}
+@tab R/W @tab
+@code{CAL_DMTD}
+@tab @code{0} @tab 
+Produce DDMTD calibration pattern (type 2 calibration)
+@item @code{6...3}
+@tab R/W @tab
+@code{PSEL}
+@tab @code{0} @tab 
+Calibration pulse output select/mask
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{CAL_PULSE} @tab Triggers generation of a calibration pulse on selected channels. Used to determine the exact 4/8ns setting tap of the fine delay line.@* write 1: immediately generates a single calibration pulse on the TDC start input and the output channels selected in the PSEL field.@* write 0: no effect.@* @b{Note:} In order for the pulse to be tagged by the TDC, it must be driven in the BYPASS mode and properly configured (I-mode, see driver/test program).
+@item @code{CAL_PPS} @tab Drives the TDC stop input with a PPS signal synchronous to the FD core's timebase:@* write 1: feeds TDC input with internally generated PPS signal.@* write 0: PPS generation disabled.@* @b{Note:} Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.
+@item @code{CAL_DMTD} @tab Controls DDMTD test pattern generation:@* write 1: enables DMTD test pattern on the TDC input and DDMTD sampling clock for the calibration flip-flops.@* write 0: DMTD pattern generation disabled.@* @b{Note:} Input multiplexer must be configured to drive the TDC trigger from the FPGA calibration output instead of the trigger input.
+@item @code{PSEL} @tab 1: enable generation of type 1 calibration pulses (@code{CALR.CAL_PULSE}) on the output corresponding to the written bit@* 0: disable pulse generation for the corresponding output 
+@end multitable
+@regsection @code{DMTR_IN} - DMTD Input Tag Register
+Provides the DDMTD tag value for the input channel (type 2 calibration).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{30...0}
+@tab R/O @tab
+@code{TAG}
+@tab @code{X} @tab 
+DMTD Tag
+@item @code{31}
+@tab R/O @tab
+@code{RDY}
+@tab @code{X} @tab 
+DMTD Tag Ready
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{TAG} @tab The tag value.
+@item @code{RDY} @tab Tag ready flag (clear-on-read):@* 1: a new DDMTD tag is available.@* 0: tag not ready yet.
+@end multitable
+@regsection @code{DMTR_OUT} - DMTD Output Tag Register
+Provides the DDMTD tag value for a selected output channel (type 2 calibration).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{30...0}
+@tab R/O @tab
+@code{TAG}
+@tab @code{X} @tab 
+DMTD Tag
+@item @code{31}
+@tab R/O @tab
+@code{RDY}
+@tab @code{X} @tab 
+DMTD Tag Ready
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{TAG} @tab The tag value.
+@item @code{RDY} @tab Tag ready flag (clear-on-read):@* 1: a new DDMTD tag is available.@* 0: tag not ready yet.
+@end multitable
+@regsection @code{ADSFR} - Acam Scaling Factor Register
+Scaling factor between the FD's internal time scale and the ACAM's format. Used only in normal operating mode (@code{GCR.BYPASS == 0}).@* Formula (for G-Mode): @code{ADSFR = round(2097.152 * ACAM_bin_size [ps])}
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{17...0}
+@tab R/W @tab
+@code{ADSFR}
+@tab @code{0} @tab 
+ADSFR Value
+@end multitable
+@regsection @code{ATMCR} - Acam Timestamp Merging Control Register
+Controls merging of fine timestamps prouced by Acam with coarse timestamps obtained by the FPGA. 
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/W @tab
+@code{C_THR}
+@tab @code{0} @tab 
+Coarse threshold
+@item @code{30...8}
+@tab R/W @tab
+@code{F_THR}
+@tab @code{0} @tab 
+Fine threshold
+@end multitable
+@regsection @code{ASOR} - Acam Start Offset Register
+ACAM timestamp start offset. Value that gets subtracted from ACAM's timestamps (due to ACAM's ALU architecture that does not support negative numbers).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{22...0}
+@tab R/W @tab
+@code{OFFSET}
+@tab @code{0} @tab 
+Start Offset
+@end multitable
+@regsection @code{IECRAW} - Raw Input Events Counter Register
+TDC debugging & statistics register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{IECRAW}
+@tab @code{X} @tab 
+Number of raw events.
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{IECRAW} @tab Number of all input pulses detected by the timestamper.
+@end multitable
+@regsection @code{IECTAG} - Tagged Input Events Counter Register
+TDC debugging & statistics register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{IECTAG}
+@tab @code{X} @tab 
+Number of tagged events
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{IECTAG} @tab Number of all input pulses which passed width/glitch checks and were correctly timestamped.
+@end multitable
+@regsection @code{IEPD} - Input Event Processing Delay Register
+TDC debugging & statistics register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{RST_STAT}
+@tab @code{0} @tab 
+Reset stats
+@item @code{8...1}
+@tab R/O @tab
+@code{PDELAY}
+@tab @code{X} @tab 
+Processing delay
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{RST_STAT} @tab Write 1: resets the delay/pulse count counters (@code{IECRAW}, @code{IECTAG} and @code{IEPD.PDELAY})@* write 0: no effect
+@item @code{PDELAY} @tab Worst-case delay between an input event and its timestamp being available. Expressed as a number of 125 MHz clock cycles.
+@end multitable
+@regsection @code{SCR} - SPI Control Register
+Single control register for the SPI Controller, allowing for atomic updates of the DAC, GPIO and PLL.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{23...0}
+@tab R/W @tab
+@code{DATA}
+@tab @code{X} @tab 
+Data
+@item @code{24}
+@tab R/W @tab
+@code{SEL_DAC}
+@tab @code{0} @tab 
+Select DAC
+@item @code{25}
+@tab R/W @tab
+@code{SEL_PLL}
+@tab @code{0} @tab 
+Select PLL
+@item @code{26}
+@tab R/W @tab
+@code{SEL_GPIO}
+@tab @code{0} @tab 
+Select GPIO
+@item @code{27}
+@tab R/O @tab
+@code{READY}
+@tab @code{X} @tab 
+Ready flag
+@item @code{28}
+@tab R/W @tab
+@code{CPOL}
+@tab @code{0} @tab 
+Clock Polarity
+@item @code{29}
+@tab W/O @tab
+@code{START}
+@tab @code{0} @tab 
+Transfer Start
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{DATA} @tab Data to be read/written from/to the SPI bus
+@item @code{SEL_DAC} @tab write 1: selects the DAC as the target peripheral of the transfer@* write 0: no effect
+@item @code{SEL_PLL} @tab write 1: selects the AD9516 PLL as the target peripheral of the transfer@* write 0: no effect
+@item @code{SEL_GPIO} @tab write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer@* write 0: no effect
+@item @code{READY} @tab read 0: SPI controller is busy performing a transfer@* read 1: SPI controller has finished its previous transfer. Read-back data is available in @code{SCR.DATA}
+@item @code{CPOL} @tab 0: SPI clock is not inverted (data valid on rising edge)@* 1: SPI clock is inverted (data valid on falling edge)
+@item @code{START} @tab write 1: starts SPI transfer from/to the selected peripheral@* write 0: no effect
+@end multitable
+@regsection @code{RCRR} - Reference Clock Rate Register
+Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way or to measure tuning range of the local VCXO.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{RCRR}
+@tab @code{X} @tab 
+Frequency
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{RCRR} @tab Reference clock frequency, in Hz
+@end multitable
+@regsection @code{TSBCR} - Timestamp Buffer Control Register
+Controls timestamp readout from the core's circular buffer
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{4...0}
+@tab R/W @tab
+@code{CHAN_MASK}
+@tab @code{0} @tab 
+Channel mask
+@item @code{5}
+@tab R/W @tab
+@code{ENABLE}
+@tab @code{0} @tab 
+Buffer enable
+@item @code{6}
+@tab W/O @tab
+@code{PURGE}
+@tab @code{0} @tab 
+Buffer purge
+@item @code{7}
+@tab W/O @tab
+@code{RST_SEQ}
+@tab @code{0} @tab 
+Reset timestamp sequence number
+@item @code{8}
+@tab R/O @tab
+@code{FULL}
+@tab @code{X} @tab 
+Buffer full
+@item @code{9}
+@tab R/O @tab
+@code{EMPTY}
+@tab @code{X} @tab 
+Buffer empty
+@item @code{21...10}
+@tab R/O @tab
+@code{COUNT}
+@tab @code{X} @tab 
+Buffer entries count
+@item @code{22}
+@tab R/W @tab
+@code{RAW}
+@tab @code{0} @tab 
+RAW readout mode enable
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{CHAN_MASK} @tab Selects which channels' time tags shall be written to the buffer. @* bit @code{0}: TDC input@* bits @code{1..4}: = Delay outputs
+@item @code{ENABLE} @tab Enables/disables timestamp readout:@* 1: timestamp buffer is enabled. Readout is possible.@* 0: timestamp buffer is disabled. Timestamps are processed (if set in delay mode), but discarded for readout.
+@item @code{PURGE} @tab write 1: clear timestamp buffer.@* write 0: no effect
+@item @code{RST_SEQ} @tab write 1: reset timestamp sequence number counter@* write 0: no effect
+@item @code{FULL} @tab read 1: buffer is full. Oldest timestamps (at the end of the buffer) are discarded as the new ones are coming.
+@item @code{EMPTY} @tab read 1: buffer is empty.@* read 0: there is some data in the buffer.
+@item @code{COUNT} @tab Number of timestamps currently stored in the readout buffer
+@item @code{RAW} @tab Enables raw timestamp readout mode (i.e. bypassing postprocessing). Used only for debugging purposes.@* write 1: enable raw mode@* write 0: disable raw mode (normal operation)
+@end multitable
+@regsection @code{TSBIR} - Timestamp Buffer Interrupt Register
+Controls the behaviour of the core's readout interrupt (coalescing).
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{9...0}
+@tab R/W @tab
+@code{TIMEOUT}
+@tab @code{0} @tab 
+IRQ timeout [milliseconds]
+@item @code{21...10}
+@tab R/W @tab
+@code{THRESHOLD}
+@tab @code{0} @tab 
+Interrupt threshold
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{TIMEOUT} @tab The IRQ line will be asserted after @code{TSBIR.TIMEOUT} milliseconds even if the amount of data in the buffer is below @code{TSBIR.THRESHOLD}.
+@item @code{THRESHOLD} @tab Minimum number of samples (timestamps) in the buffer that immediately triggers an interrupt.
+@end multitable
+@regsection @code{TSBR_SECH} - Timestamp Buffer Readout Seconds Register (MSB)
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/O @tab
+@code{TSBR_SECH}
+@tab @code{X} @tab 
+Timestamps TAI Seconds (bits 39-32)
+@end multitable
+@regsection @code{TSBR_SECL} - Timestamp Buffer Readout Seconds Register (LSB)
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{TSBR_SECL}
+@tab @code{X} @tab 
+Timestamps TAI Seconds (bits 31-0)
+@end multitable
+@regsection @code{TSBR_CYCLES} - Timestamp Buffer Readout Cycles Register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/O @tab
+@code{TSBR_CYCLES}
+@tab @code{X} @tab 
+Timestamps cycles count (in 8 ns ticks)
+@end multitable
+@regsection @code{TSBR_FID} - Timestamp Buffer Readout Fine/Channel/Sequence ID Register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{3...0}
+@tab R/O @tab
+@code{CHANNEL}
+@tab @code{X} @tab 
+Channel ID
+@item @code{15...4}
+@tab R/O @tab
+@code{FINE}
+@tab @code{X} @tab 
+Fine Value (in phase units)
+@item @code{31...16}
+@tab R/O @tab
+@code{SEQID}
+@tab @code{X} @tab 
+Timestamp Sequence ID
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{CHANNEL} @tab ID of the originating channel:@* @code{0}: TDC input@* @code{1..4}: outputs 1..4
+@end multitable
+@regsection @code{I2CR} - I2C Bit-banged IO Register
+Controls state of the mezzanine's I2C bus lines by means of bitbanging
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/W @tab
+@code{SCL_OUT}
+@tab @code{1} @tab 
+SCL Line out
+@item @code{1}
+@tab R/W @tab
+@code{SDA_OUT}
+@tab @code{1} @tab 
+SDA Line out
+@item @code{2}
+@tab R/O @tab
+@code{SCL_IN}
+@tab @code{X} @tab 
+SCL Line in
+@item @code{3}
+@tab R/O @tab
+@code{SDA_IN}
+@tab @code{X} @tab 
+SDA Line in
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{SCL_OUT} @tab write 0: drive SCL to 0 @* write 1: drive SCL to weak 1 (pullup)
+@item @code{SDA_OUT} @tab write 0: drive SDA to 0 @* write 1: drive SDA to weak 1 (pullup)
+@item @code{SCL_IN} @tab State of the SCL line.
+@item @code{SDA_IN} @tab State of the SDA line.
+@end multitable
+@regsection @code{TDER1} - Test/Debug Register 1
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{VCXO_FREQ}
+@tab @code{X} @tab 
+VCXO Frequency
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{VCXO_FREQ} @tab Mezzanine VCXO frequency in Hz, measured using the system clock as a reference. Used during factory test only.
+@end multitable
+@regsection @code{TDER2} - Test/Debug Register 1
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/W @tab
+@code{PELT_DRIVE}
+@tab @code{0} @tab 
+Peltier PWM drive
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{PELT_DRIVE} @tab Peltier module PWM drive. Lab-only feature for measuring temperature characteristics of the board.
+@end multitable
+@regsection @code{TSBR_DEBUG} - Timestamp Buffer Debug Values Register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/O @tab
+@code{TSBR_DEBUG}
+@tab @code{X} @tab 
+Debug value
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{TSBR_DEBUG} @tab Additional register for holding timestamp debug data (used only in raw readout mode). Content format is not specified.
+@end multitable
+@regsection @code{TSBR_ADVANCE} - Timestamp Buffer Advance Register
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{ADV}
+@tab @code{0} @tab 
+Advance buffer readout
+@end multitable
+@regsection @code{EIC_IDR} - Interrupt disable register
+Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{TS_BUF_NOTEMPTY}
+@tab @code{0} @tab 
+Timestamp Buffer interrupt.
+@item @code{1}
+@tab W/O @tab
+@code{DMTD_SPLL}
+@tab @code{0} @tab 
+DMTD SoftPLL interrupt
+@item @code{2}
+@tab W/O @tab
+@code{SYNC_STATUS}
+@tab @code{0} @tab 
+Sync Status Changed
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{ts_buf_notempty} @tab write 1: disable interrupt 'Timestamp Buffer interrupt.'@*write 0: no effect
+@item @code{dmtd_spll} @tab write 1: disable interrupt 'DMTD SoftPLL interrupt'@*write 0: no effect
+@item @code{sync_status} @tab write 1: disable interrupt 'Sync Status Changed'@*write 0: no effect
+@end multitable
+@regsection @code{EIC_IER} - Interrupt enable register
+Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab W/O @tab
+@code{TS_BUF_NOTEMPTY}
+@tab @code{0} @tab 
+Timestamp Buffer interrupt.
+@item @code{1}
+@tab W/O @tab
+@code{DMTD_SPLL}
+@tab @code{0} @tab 
+DMTD SoftPLL interrupt
+@item @code{2}
+@tab W/O @tab
+@code{SYNC_STATUS}
+@tab @code{0} @tab 
+Sync Status Changed
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{ts_buf_notempty} @tab write 1: enable interrupt 'Timestamp Buffer interrupt.'@*write 0: no effect
+@item @code{dmtd_spll} @tab write 1: enable interrupt 'DMTD SoftPLL interrupt'@*write 0: no effect
+@item @code{sync_status} @tab write 1: enable interrupt 'Sync Status Changed'@*write 0: no effect
+@end multitable
+@regsection @code{EIC_IMR} - Interrupt mask register
+Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/O @tab
+@code{TS_BUF_NOTEMPTY}
+@tab @code{X} @tab 
+Timestamp Buffer interrupt.
+@item @code{1}
+@tab R/O @tab
+@code{DMTD_SPLL}
+@tab @code{X} @tab 
+DMTD SoftPLL interrupt
+@item @code{2}
+@tab R/O @tab
+@code{SYNC_STATUS}
+@tab @code{X} @tab 
+Sync Status Changed
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{ts_buf_notempty} @tab read 1: interrupt 'Timestamp Buffer interrupt.' is enabled@*read 0: interrupt 'Timestamp Buffer interrupt.' is disabled
+@item @code{dmtd_spll} @tab read 1: interrupt 'DMTD SoftPLL interrupt' is enabled@*read 0: interrupt 'DMTD SoftPLL interrupt' is disabled
+@item @code{sync_status} @tab read 1: interrupt 'Sync Status Changed' is enabled@*read 0: interrupt 'Sync Status Changed' is disabled
+@end multitable
+@regsection @code{EIC_ISR} - Interrupt status register
+Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{0}
+@tab R/W @tab
+@code{TS_BUF_NOTEMPTY}
+@tab @code{X} @tab 
+Timestamp Buffer interrupt.
+@item @code{1}
+@tab R/W @tab
+@code{DMTD_SPLL}
+@tab @code{X} @tab 
+DMTD SoftPLL interrupt
+@item @code{2}
+@tab R/W @tab
+@code{SYNC_STATUS}
+@tab @code{X} @tab 
+Sync Status Changed
+@end multitable
+@multitable @columnfractions 0.15 0.85
+@headitem Field @tab Description
+@item @code{ts_buf_notempty} @tab read 1: interrupt 'Timestamp Buffer interrupt.' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Timestamp Buffer interrupt.'@*write 0: no effect
+@item @code{dmtd_spll} @tab read 1: interrupt 'DMTD SoftPLL interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMTD SoftPLL interrupt'@*write 0: no effect
+@item @code{sync_status} @tab read 1: interrupt 'Sync Status Changed' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Sync Status Changed'@*write 0: no effect
+@end multitable
--- a/doc/design-notes/fine-delay.in
+++ b/doc/design-notes/fine-delay.in
@@ -33,7 +33,7 @@
 @paragraphindent 3
 @comment %**end of header

-@setchapternewpage off
+@setchapternewpage on

 @set update-month December 2012

@@ -41,7 +41,7 @@

 @titlepage
 @title Fine Delay Design Notes
-@subtitle FMC Delay 1ns-4cha
+@subtitle June 2013
 @author CERN BE-CO-HT / Tomasz Włostowski

 @end titlepage
@@ -67,54 +67,57 @@
 @chapter Introduction

 This document contains some detailed information on the hardware design of the
-Fine Delay Mezzanine (further abbeviated as the FD) and its VHDL core.
+Fine Delay Mezzanine (also called FmcDelay1ns4cha and further abbeviated as the FD) and its VHDL core.
 It is not very useful for the FD's users and it is certainly not formal. 
 Its target are driver developers, carrier/hardware integrators,
 people interested in building similar devices and looking for hints and inspiration
 or the folks curious why something was done in that and not another way. It also explains
 things that are not obvious in the VHDL/test program code, such as the calibration mechanisms
-and ACAM's TDC quirks.
+and Acam's TDC quirks.

-The hardware/HDL description contains very frequent references the card's schematics, PCB design and VHDL sources. It is a good idea to print or open them before continuing reading (@xref{References}).
+The hardware/HDL description contains very frequent references to the card's schematics [1], PCB design and VHDL sources [3]. It is a good idea to print or open them before continuing reading.
+
+Note that this description refers to the latest version of the hardware, that is EDA-02267-V5-2. It can be considered almost accurate for the versions since V3-0. Future and past improvements to the hardware can be found in the @i{Issues} section of the project's Wiki [3].

 @page
 @chapter The Hardware

 @section Overview

-The FD is a VITA-57 FPGA Mezzanine card, whose basic function is taking TTL pulses and reproducing them on one or more of 4 TTL
+The FD is a VITA-57 LPC FPGA Mezzanine card, whose basic function is taking TTL pulses and reproducing them on one or more of four TTL
 outputs after a given time. Delay can be programmed to any value between 600 ns and 12 seconds with 10 ps resolution. 
 It is also possible to control width, spacing and repetition rate of the output pulses. 
-The exact specifications can be found in the official User's Manual.
+The exact, detailed specifications can be found in the User's Manual.

 @float Figure,fig:fd_block
 @center @image{drawings/block_diagram, 15cm,,,.pdf}
 @caption{Block diagram of a FD card.}
 @end float

-The FD's principle of operation is explained in @ref{fig:fd_simple}. The card time tags an input pulse (using a Time-to-Digital converter),
-adds the desired delay to the time tag and produces a pulse on the output when the internal time base counter hits 
-the computed sum. The fine part (that is, less than a single clock cycle) is adjusted by an external programmable delay line.
+@ref{fig:fd_block} depicts a detailed hardware block diagram of the FD. The major design blocks are:
+@itemize
+@item The TDC, built with the Acam's TDC-GPX chip.
+@item Output stages, based on LVPECL '195 programmable delay chips.
+@item Clock distribution circuit, encompassing a multi-output PLL synthesizer (AD9516).
+@item Power supplies, SPI general-purpose IO, sensors and ID EEPROM.
+@end itemize

 @float Figure,fig:fd_simple
 @center @image{drawings/simple_diagram, 15cm,,,.pdf}
 @caption{Simplified principle of FD operation.}
 @end float

-@ref{fig:fd_block} depicts a detailed hardware block diagram of the FD. The major design blocks are:
-@itemize
-@item The TDC, built with the Acam's TDC-GPX chip,
-@item Output stages, based on LVPECL '195 programmable delay chips,
-@item Clock distribution circuit, encompassing a multi-output PLL synthesizer (AD9516),
-@item Power supplies, SPI general-purpose IO, sensors and ID EEPROM.
-@end itemize
+The FD's principle of operation is explained in @ref{fig:fd_simple}. The card time tags an input pulse (using a Time-to-Digital converter),
+adds the desired delay to the time tag and produces a pulse on the output when the internal time base counter hits the computed sum. The fine part (that is, less than a single clock cycle) is adjusted by an external programmable delay line.
+
+

 @section Clock distribution

 Relevant files: @code{clock_generator.SchDoc}

 The FD requires a number of different clock signals to synchronize the TDC,
-the output stages and the FPGA core altogether. All clocks are generated by the Analog Devices`
+the output stages and the FPGA core altogether. All clocks are generated by the Analog Devices'
 AD9516-4 integrated PLL/clock fanout (IC4). This particular chip was chosen due to its wide 
 configuration capabilities (frequency settings, fine per-output phase adjustment), support 
 for multiple I/O standards (PECL, single-ended, etc) and low inter-output skew. 
@@ -122,23 +125,22 @@ The PLL outputs are programmed as follows:
 @itemize
 @item OUT9: 125 MHz FPGA reference clock (LVDS). The choice of 125 MHz reference is forced 
 by compliance with White Rabbit and Gigabit Ethernet for distributed, 
-sub-nanoseconds synchronization of multiple cards. All other clocks used in the design 
-are derived from 125 MHz.
+sub-nanosecond synchronization of multiple cards. All other clocks used in the design 
+are derived from 125@tie{}MHz.
 @item OUT0..3: 250 MHz clocks that drive the output flip flops. The frequency value 
 comes from the functional requirement for generation of 10 MHz, WR-aligned clock - 250 MHz is the 
 smallest common multiple of both 10 MHz and 125 MHz WR clock. Note that outputs 0, 1 and 2 are inverted to
 simplify PCB routing (this is compensated by AD9516's programmable output polarity control).
 @item OUT7: 31.25 Mhz TDC reference clock (LVCMOS). Must be lower than the TDC maximum 
 reference frequency (40 MHz) and an integer fraction of 125 MHz. 31.25 MHz is the largest
-possible value. Too low value would significantly reduce TDC throughput.
+possible value. Low value would significantly reduce TDC throughput and increase timestamping latency, as it clocks the Acam's internal timestamp processing pipeline.
 @item OUT4, OUT5: 7.8125 MHz TDC start signals (LVPECL to the TDC, LVCMOS to the FPGA). 
 Rising edges of these clocks are the reference points for time interval measurement in the TDC. The TDC start signal
-is further divided by 2 (by toggling TDC's @code{StartDis} pin) to avoid exceeding ACAM's maximum start frequency of 7 MHz. Unfortunately it
+is further divided by two (by toggling TDC's @code{StartDis} pin) to avoid exceeding Acam's maximum start frequency of 7 MHz. Unfortunately it
 is not possible to achieve higher division ratios directly in the PLL chip.
 @end itemize

-AD9516's PLL bandwidth is set to approx. 10 kHz by the loop filter components (R41, C33 and neighbours), resulting in optimal phase noise distribution. The PLL is referenced 
-to a 25 MHz VCTCXO OSC5, a Mercury Crystal VM53S3-series oscillator. The TCXO can be digitally
+The AD9516's PLL bandwidth is set to approx. 10 kHz by the loop filter components (R41, C33 and neighbours), whose values were calculated using Analog Devices @i{AdiSimClk} software [11] with default performance settings (the jitter of the TDC and output stages is an order of magnitude larger than worst-case jitter of the AD9516 PLL). The PLL is referenced to a 25 MHz VCTCXO OSC5, a Mercury Crystal VM53S3-series oscillator. The TCXO can be digitally
 tuned within (±10 ppm) range by the 16-bit  DAC IC14 (AD5662). Low-cost shunt regulator IC10 
 (LM336) provides the reference voltage for the DAC (it needs not be extremely stable because the 
 whole circuit usually works in a feedback loop, see @ref{fig:wr_pll}). The combination 
@@ -146,7 +148,7 @@ of the used DAC and oscillator meets the requirements of Synchronous Ethernet an
 for synchronization: 1kHz PLL bandwidth and tuning sensitivity of < 1 ppb and range of > ±2.5 ppm. 
 Careful readers should have noticed at this point that it is not possible to directly feed an 
 external reference clock to the card. This limitation is caused by the lack of carrier to 
-mezzanine clock signals in low pin version of an FMC connector and is solved by locking 
+mezzanine clock signals in the low pin version of an FMC connector and is solved by locking 
 the cards' clock to the the external frequency with a PLL implemented in the carrier FPGA. 

 The PLL is powered from 3.3V filtered by an LC circuit (L3 and its surroundings), following 
@@ -162,11 +164,11 @@ The role of the input stage is to adapt the incoming trigger pulses so that they
 by the TDC and the FPGA. Following the signal path starting from the input connector:
 @itemize
 @item fuse F5 protects the input stage against a serious overvoltage/overcurrent 
-(e.g. connecting the input to a 12 V DC power supply)
+(e.g. connecting the input to a 12 V DC power supply).
 @item resistors R110, R116, R117 along with the MOSFET T2 constitute a programmable 
 50 Ohm termination. 3 resistors connected in parallel were used to give more freedom
 for the PCB designer (the board is packed quite tightly) and ease power dissipation. 
-R76 ensures calibration mode is off by default. 
+R76 ensures calibration mode is off by default.
 @item PIN diodes D6 (BAR66) and resistor R57 form a fast overvoltage clamping circuit. 
 R57 reduces the D6's clamping current (~200 mA) for small overloads, clamping currents 
 above 200 mA will anyway blow the fuse F5. R108 pulls down the input, lowering its impedance 
@@ -174,7 +176,7 @@ and preventing an unconnected input from taking glitches/EMI as legitimate trigg
 @item FET switch IC18 (TS3USB221) selects the signal that drives the TDC input 
 between the trigger input and a calibration line driven by the FPGA (the calibration process
 will be discussed later). @code{TRIG_SEL} line selects the active input (by default, it's the LEMO trigger connector).
-@item Output of the switch feeds 3 other components: an LVTTL to LVPECL buffer (IC5, 100EPT29), 
+@item The output of the switch IC18 feeds three other components: an LVTTL to LVPECL buffer (IC5, 100EPT29), 
 which drives the TDC's Stop input, an LVCMOS buffer (IC23, LVC125) that feeds the trigger signal
 to the FPGA and a single-gate D flip flop which takes part in the DDMTD calibration. The physical length of the signal path between these components 
 is very short (5mm on the PCB) to avoid stubs and reflections.
@@ -191,9 +193,9 @@ between two inputs, called Start and Stop. The start input is used to provide th
 (i.e. pulses occuring at well defined moments in time) and the stop input takes the
 pulses to be timestamped.

-The FD's TDC is a single-chip solution, called TDC-GPX, made by Acam (IC8). It can simultaneously 
+The FD's TDC is a single-chip solution, called TDC-GPX, made by Acam (IC8) [5]. It can simultaneously 
 timestamp from 1 to 8 inputs, with accuracy and repetition rate depending on the mode of 
-operation (R, I, M, G-modes, more details in the TDC-GPX datasheet). In the FD, the ACAM serves two purposes:
+operation (R, I, M, G-modes, more details in the TDC-GPX datasheet). In the FD, the Acam serves two purposes:
 @itemize
 @item The obvious one: @b{time tagging trigger pulses}. The TDC in configured in the G-mode, with a single
 stop input, providing 7 Mpulses/second throughput, measurement range of 40 us and resolution (one-sigma) 
@@ -206,7 +208,7 @@ final, accurate value (@xref{Timestamp postprocessing}).

 @item @b{Calibration} of the output delay lines, done during initialization 
 of the card. Its goal is to determine the setpoint for each delay line that results with a delay of exactly 8 ns 
-(single reference clock cycle), and thus compensates the PVT effects. The TDC is working in the I-mode 
+(single reference clock cycle), and thus compensates the @i{Process-Voltage-Temperature} (PVT) effects. The TDC is working in the I-mode 
 (81 ps resolution), with one LVTTL start connected to an FPGA output generating arbitrary pulses and 
 the 4 LVTTL stop inputs wired to the outputs of the delay chips (@xref{Output stage calibration}). 
 @end itemize
@@ -227,7 +229,7 @@ Unfortunately, in @i{The Real World}, PVT
 effects come into play, causing the delay introduced by each buffer to vary with temperature, 
 voltage and between different chips. The TDC by Acam employs a clever trick to compensate for this 
 delay spread. It has another delay line, with more or less identical silicon layout but with 
-positive feedback, turning it into a ring oscillator. Frequency of this oscillator 
+positive feedback, turning it into a ring oscillator. The frequency of this oscillator 
 is continuously measured and compared against a reference value corresponding to the desired 
 bin size. The resulting error signal drives a servo that controls the voltage powering both the 
 oscillator and the measurement delay line(s) in such way that bin size stays constant (assuming 
@@ -235,13 +237,13 @@ that delays introduced by each of the buffers scale with very similar factors).
 why the power circuitry for the TDC is so complex (3 LM1117 LDO regulators - IC6, IC89 and IC21). 
 The servo output signal @code{PHASE} is PWM-modulated and after filtering in R17-C22-R16 and R20-C42-R22 
 circuits, set bias voltage on the ADJ pins of the regulators, which directly determine
-their output voltages (Vadj = Vout - 1.25 V). The values of the voltage divider components and 
+their output voltages (Vadj = Vout - 1.25@tie{}V). The values of the voltage divider components and 
 large number of decoupling capacitors come from the TDC-GPX reference design provided by Acam. 

 The TDC communicates with the FPGA using a simple asynchronous address/data bus, with 4 address 
 bits and 28 data bits. Aside from standard bus lines (@code{CS}, @code{RD}, @code{WR}), the FPGA drives the TDC FIFO 
 purge signal (@code{TDC_ALUTRIGGER}) and receives the Timestamp FIFO Empty and Error flags (@code{TDC_EF} and @code{TDC_ERR}).
-Series resistors on TDC data lines are provided to match impedance of the PCB traces, 
+Series resistors on TDC data lines are provided to match the impedance of the PCB traces, 
 improving signal integrity and EMC performance. 

 Note that the address inputs of the TDC are not driven by the FPGA, but by the SPI GPIO controller (MC23S17, IC19).
@@ -254,21 +256,21 @@ Relevant files: @code{delay_channel.SchDoc}, @code{output_driver.SchDoc}, @code{

 The role of the FD's output stages is to:
 @itemize
-@item reduce the jitter and de-skew coarse output pulses produced by the FPGA,
-@item adjust the fine part of the delay,
-@item properly drive a 50 Ohm load.
+@item Reduce the jitter and de-skew coarse output pulses produced by the FPGA.
+@item Adjust the fine part of the delay.
+@item Properly drive a 50 Ohm load.
 @end itemize

 The first task is done by the discrete LVPECL flip-flops (IC3). The D inputs of the FFs are
-connected to FPGA pins (output counter comparators), while the CLK inputs supply 4 low-skew
+connected to FPGA pins (output counter comparators), while the CLK inputs supply four low-skew
 250 MHz clocks, synchronous with the FPGA's reference 125 MHz clock. This way, poor quality
-pulses prouduced by the FPGA are retimed and deskewed, resulting with an output-to-output skew
+pulses produced by the FPGA are retimed and deskewed, resulting with an output-to-output skew
 of less than 100 ps and jitter level comparable to noise of the PLL chip. 

 Retimed output signals are fed to the delay lines (IC2, IC7). A SY89295 chip from
 Micrel was used, mainly because of availabilty in QFN packages (PCB space constraints). 
 The delay lines are configured by outputting the number of delay taps on @code{D0..9} and latching it in by asserting @code{LEN} input low. Value @code{0} corresponds to 2.2 ns and @code{1023} to 12.5 ns, giving
-quite a lot of headroom (we need 4 ns range). Delays are updated immediately after laching in a new value. All delay chips share
+quite a lot of headroom (we need a 4 ns range). Delays are updated immediately after laching in a new value. All delay chips share
 same data bus, which is arbitrated by the FPGA (again, due to lack of pins in the FMC connector). The price is higher minimum possible delay setpoint. Resistors R11 and R53 select the signalling
 level for the control inputs (LVTTL). 

@@ -281,7 +283,8 @@ the opamp's output and SSR's series impedances form a 50 Ohm source termination.
 The lowpass circuit R42/C49 makes sure the SSR is switched without glitching. IC26 buffers the output signal for driving feedback TDC input (calibration).
 The D flip flop IC27 is a part of DDMTD-based calibration circuit. R66 and R34 constitute a voltage divider, bringing down the 6 V output of the opamp to a level
 that is acceptable by LVC/AUP logic. Yet again, due to lack of pins, calibration flip flop outputs are ANDed together, making a trivial multiplexer (one output is calibrated at a time,
-while the rest is driven to 1). The output stage meets edge rising time requirement of 2 V/ns (thanks to extreme output voltage rise speed of AD8009 of 5.5 kV/us) for both 50 Ohm and high impedance loads and is capable of producing neat, clean pulses of 3 V level on 50 Ohms, suitable for directly driving TTL inputs (see @ref{fig:output_shape}).
+while the rest is driven to 1). The output stage meets the edge rising time requirement of 2 V/ns (thanks to the very high output voltage rise speed of AD8009 of 5.5 kV/us) for both 50 Ohm and high impedance loads and is capable of producing neat, clean pulses of 3 V level on 50 Ohms, suitable for directly driving TTL inputs (see @ref{fig:output_shape}).
+

 @page
 @float Figure,fig:output_shape
@@ -289,7 +292,25 @@ while the rest is driven to 1). The output stage meets edge rising time requirem
 @caption{Shape of an output pulse rising edge on a 50 Ohm load.}
 @end float

+@section Power supply

+The FD takes power from the following lines in the FMC connector:
+@itemize
+@item P3V3, that is used for all LVPECL/LVTTL logic on the board, including the AD9516 and TDC I/O power. Approximate current consumption is 1.5 A.
+@item P12V, used for powering the output stages and Acam's PLL. This rail draws approximately 200 mA.
+@item P3V3_AUX, powering only the configuration EEPROM (less than 5 mA).
+@end itemize
+
+Aside from the standard FMC power lines, the FD contains two dedicated switching mode power converters:
+@itemize
+@item The buck converter IC11 for +8 V / 600 mA supply, powering the output stage opamps and Acam's PLL linear regulators. The TVS diode D7 provides additional overvoltage protection for the outputs (when a high current DC voltage is connected, D7 clips it to a safe level, because the P8V PSU is unable to sink current).
+@item The inverting converter IC30, producing -2 V @ 600 mA, used solely for powering the output driver.
+@end itemize
+
+The P8V, P3V3 and VADJ supplies are monitored by a reset/voltage supervisor IC8 (TPS3307-33), which ensures that the card is un-reset only when all supply voltages have stabilized. The VADJ rail, even though it is not used to power any part of the FD, is monitored as it powers the FPGA LVTTL/LVDS drivers in the carrier and its failure would also render the mezzanine useless. The RC circuit (R78, D1, C57) determines the power-on-reset time and deglitches the reset signal coming from the FMC connector.
+
+The average power dissipation of the FD is approximately 7 - 7.5 W, being large enough to heat the PCB to 60 - 70 @textdegree C in poorly cooled environments such as Kontron KISS PCs. Forced airflow is required. In order to increase the card reliability in high temperatures, all non-ceramic capacitors (single type in the project: 10 uF/16 V) are Sanyo Poscap TQC series, rated 200000 hours at 65 @textdegree C.
+@page
 @section Everything else

 Relevant files: @code{FMC_Delay_1ns_4cha.SchDoc}.
@@ -301,36 +322,31 @@ plug for more important purposes. These signals are: TDC address lines, output s
 calibration mode select and termination enable. See table below for GPIO pin mapping:
 @multitable  @columnfractions .20 .80
 @headitem GPIO pin @tab Signal
-@item @code{A0} @tab Input termination enable (active hi)
-@item @code{A2} @tab Output 4 enable (active hi)
-@item @code{A3} @tab Output 3 enable (active hi)
-@item @code{A4} @tab Output 2 enable (active hi)
-@item @code{A5} @tab Output 1 enable (active hi)
+@item @code{A0} @tab Input termination enable (active high)
+@item @code{A2} @tab Output 4 enable (active high)
+@item @code{A3} @tab Output 3 enable (active high)
+@item @code{A4} @tab Output 2 enable (active high)
+@item @code{A5} @tab Output 1 enable (active high)
 @item @code{A6} @tab Trigger select (0 = external, 1 = FPGA)
-@item @code{B0} @tab ACAM address bit @code{0}
-@item @code{B1} @tab ACAM address bit @code{1} 
-@item @code{B2} @tab ACAM address bit @code{2}
-@item @code{B3} @tab ACAM address bit @code{3}
+@item @code{B0} @tab Acam address bit @code{0}
+@item @code{B1} @tab Acam address bit @code{1} 
+@item @code{B2} @tab Acam address bit @code{2}
+@item @code{B3} @tab Acam address bit @code{3}
 @end multitable
 @item Buffers (IC12, IC28, IC29 - LVC1G125): ensure correct operation of all SPI peripherals by 
-adapting 2.5 V LVCMOS levels from the FPGA to 3.3 V LVTTL,
+adapting 2.5 V LVCMOS levels from the FPGA to 3.3 V LVTTL.
 @item Buffers (IC32, IC31 - LVC1G125): boost output current & voltage levels of the FPGA for driving calibration
-inputs (DDMTD clock and calibration TDC pulses), 
+inputs (DDMTD clock and calibration TDC pulses).
 @item 1-Wire temperature sensor (IC13, DS18B20U+): measures the temperature of the output delay lines 
 (used by on-the-fly delay drift compensation) and gives each board a unique ID number.
 @item Two LEDs and a configiuration EEPROM (IC22) - standard components of every FMC card. The EEPROM is also used for storage of calibration parameters.
-@item Power supply: the FD includes two switching PSUs: a buck converter IC11 for +8 V / 600 mA supply and an inverting converter IC30, producing -2 V @ 600 mA. Both converters are solely for
-powering the output stage opamps. 
-@item Voltage supervisor IC36 (TPS3307-33) - ensures that the card is un-reset only after all supply voltages have stabilized. 
-@item Slow power-on-reset circuit (R78, D1, C57).
-@item TVS diode D7: additional overvoltage protection for outputs (when a high current DC voltage is connected, D7 clips it to a safe level, because P8V PSU is unable to sink current).
 @end itemize


 @page
 @chapter The VHDL

-This chapter provides a brief description of the VHDL design of the FD core. For more detailed explanations, you may need to refer to the comments in the source code (see @xref{References}). 
+This chapter provides a brief description of the VHDL design of the FD core. For more detailed explanations, you may need to refer to the comments in the source code [3]. 

 @section Core interface

@@ -353,14 +369,14 @@ The table below lists all I/O ports of the VHDL FD core and the corresponding ne
 @item @code{dmtd_samp_o} @tab output @tab DDMTD calibration flip-flop clock @tab @code{DMTD_CLK}
 @item @code{led_trig_o} @tab output @tab Trigger LED @tab @code{LED_TRIG}
 @item @code{ext_rst_n_o} @tab output @tab FMC hardware reset line @tab @code{EXT_RESET_N}
-@item @code{pll_status_i} @tab input @tab AD9516 STATUS pin @tab @code{PLL_STATUS}.
-@item @code{acam_d_o}, @code{acam_d_i}, @code{acam_d_oen_o} @tab tristate @tab ACAM data bus. Tristate enable signal is active LOW @tab @code{TDC_D}
-@item @code{acam_emptyf_i} @tab input @tab ACAM empty flag @tab @code{TDC_EF}
-@item @code{acam_alutrigger_o} @tab output @tab ACAM ALU Trigger line (used as FIFO purge signal) @tab @code{TDC_ALUTRIGGER}
-@item @code{acam_wr_n_o} @tab output @tab ACAM write enable @tab @code{TDC_WRN}
-@item @code{acam_rd_n_o} @tab output @tab ACAM read enable @tab @code{TDC_RDN}
-@item @code{acam_start_dis_o} @tab input @tab ACAM Start Disable pin @tab @code{TDC_START_DIS}
-@item @code{acam_stop_dis_o} @tab input @tab ACAM Stop Disable pin @tab @code{TDC_STOP_DIS}
+@item @code{pll_status_i} @tab input @tab AD9516 STATUS pin @tab @code{PLL_STATUS}
+@item @code{acam_d_o}, @code{acam_d_i}, @code{acam_d_oen_o} @tab tristate @tab Acam data bus. Tristate enable signal is active LOW @tab @code{TDC_D}
+@item @code{acam_emptyf_i} @tab input @tab Acam empty flag @tab @code{TDC_EF}
+@item @code{acam_alutrigger_o} @tab output @tab Acam ALU Trigger line (used as FIFO purge signal) @tab @code{TDC_ALUTRIGGER}
+@item @code{acam_wr_n_o} @tab output @tab Acam write enable @tab @code{TDC_WRN}
+@item @code{acam_rd_n_o} @tab output @tab Acam read enable @tab @code{TDC_RDN}
+@item @code{acam_start_dis_o} @tab input @tab Acam Start Disable pin @tab @code{TDC_START_DIS}
+@item @code{acam_stop_dis_o} @tab input @tab Acam Stop Disable pin @tab @code{TDC_STOP_DIS}
 @item @code{spi_cs_dac_n_o} @tab output @tab AD5662 DAC SPI chip select @tab @code{SPI_DAC_CSN}
 @item @code{spi_cs_pll_n_o} @tab output @tab AD9516 PLL SPI chip select @tab @code{SPI_PLL_CSN}
 @item @code{spi_cs_gpio_n_o} @tab output @tab MCP23S17 GPIO SPI chip select @tab @code{SPI_IO_CSN}
@@ -421,15 +437,15 @@ Relevant files: @code{fine_delay_core.vhd}, @code{fine_delay_pkg.vhd}.

 The top level diagram of the FD core is shown in @ref{fig:hdl_top}. Its major components are:
 @itemize
-@item ACAM timestamper unit, producing time tags for input pulses,
-@item 4 FD channel drivers, which take these time tags, add the desired delay and produce a number pulses of given width and spacing,
-@item Platform-specfic DDR drivers,
-@item Ring buffer, providing timestamps of input/output pulses for the host system,
-@item Time base and reset generators, calibration logic and peripheral I/O cores (Onewire, etc.)
+@item Acam timestamper unit, producing time tags for input pulses.
+@item 4 FD channel drivers, which take these time tags, add the desired delay and produce a number pulses of given width and spacing.
+@item Platform-specfic dual-edge (DDR) output flip-flops.
+@item Ring buffer, providing timestamps of input/output pulses for the host system.
+@item Time base and reset generators, calibration logic and peripheral I/O cores (e.g. Onewire).
 @end itemize
-All of these are accessible from the host via a Wishbone bus. There are 6 Wishbone slaves in the design: 4 output register banks (one per each channel driver),
-the main register bank (shared between all other sub-cores) and a 3rd-party OneWire core. Custom register banks were generated using the @code{wbgen2} tool. 
-An SDB descriptor is provided for plug&play integration on the carrier with other cores. @xref{References} for more information on @code{wbgen2} and SDB. 
+All of these are accessible from the host via a Wishbone bus. There are six Wishbone slaves in the design: 4 output register banks (one per each channel driver),
+the main register bank (shared between all other sub-cores) and a 3rd-party OneWire core. Custom register banks were generated using the @code{wbgen2} tool [12]. 
+An SDB descriptor is provided for plug&play integration on the carrier with other cores [9]. 

 Aside from the Wishbone registers, the FD core provides direct timestamp I/O ports, which can be used to easily collect timestamps and trigger output pulses from other cores in your design. Note that in order to use the direct I/O it is still necessary to program the core and the TDC via Wishbone. 

@@ -449,8 +465,8 @@ references the entire pulse processing path (TDC core, output drivers, calibrati

 The time base for the FD core is provided by the @code{fd_csync_generator} unit. By ``time base'', we mean the the signals representing the core's internal notion of time, which are synchronous to the reference clock @code{clk_ref_0}:
 @itemize
-@item @code{csync_utc}: TAI seconds,
-@item @code{csync_coarse}: number of @code{clk_ref_0} cycles since beginning of the current second,
+@item @code{csync_utc}: TAI seconds.
+@item @code{csync_coarse}: number of @code{clk_ref_0} cycles since beginning of the current second.
 @item @code{csync_pps}: Pulse-per-second signal, generated 3 cycles in advance, to accommodate for pipeline delays in the TDC and output drivers.
 @end itemize

@@ -459,7 +475,7 @@ Timing-wise, the FD can work in two modes:
 @item @b{Local time base} mode, where @code{clk_ref_0} oscillator is free running and the time counters 
 are coarsely initialized by the host through @code{TM_SECH}, @code{TM_SECL}, @code{TM_COARSE} and @code{TCR} registers. 
 In this mode, the TDC input/output events cannot be very accurately related to other cores/devices, 
-and the delay accuracy is as good as of the local oscillator (±2.5 ppm), 
+and the delay accuracy is as good as of the local oscillator (±2.5@tie{}ppm), 
 which means worst case error of 2.5 ns for a delay setting of 1 ms.
 @item @b{White Rabbit time base} mode, in which the reference clock is phase-locked to the WR master clock (by means of the SoftPLL
 inside the WR Core) and the time base signals are following the second/cycles counters provided by the WR Core 
@@ -476,24 +492,23 @@ Mode selection is controlled by the @code{TCR} register and the @code{p_whiterab
 which also informs driver about the status of WR/local operation and can generate interrupts whenever the state 
 of the synchronization source changes. When the WR link goes down, the FSM automatically
 switches the card to local time base mode, retaining the previous value of time base counters 
-(so the time will slowly drift away from the WR time scale, but not ``jump''). There is no 
-automatic local-to-WR switchover available yet, it must be done manually from the host. Loss or acquisition of WR synchronization is signalled to the host via @code{TCR} status bits and an interrupt.
+(so the time will slowly drift away from the WR time scale, but not ``jump''). In case of the WR link recovery after a failure, the resynchronization procedure must be triggered by the host (no seamless, automatic switchover yer - see issue @i{769} in [3]). Loss or acquisition of WR synchronization is signalled to the host via @code{TCR} status bits or an interrupt.

 @section The TDC block
 Relevant files: @code{fd_acam_timestamper.vhd}, @code{fd_acam_timestamp_postprocessor.vhd}, @code{fd_timestamper_stat_unit.vhd}.

-The TDC controller interfaces with the ACAM TDC-GPX chip and does whatever is neccessary to output timestamps aligned with the FD core's time base, as fast (in terms of delay) as possible. That is:
+The TDC controller interfaces with the Acam TDC-GPX chip and does whatever is neccessary to output timestamps aligned with the FD core's time base, as fast (in terms of delay) as possible. That is:
 @itemize
-@item detection of input pulses, checking their width and generation of coarse (256 ns granularity) timestamps by taking a snapshot of an internal counter,
-@item reading out the fine part from the ACAM,
-@item merging these values together, aligning the result to the local timebase and outputting everything in a format digestible by the pulse generators.
+@item Detection of input pulses, checking their width and generation of coarse (256 ns granularity) timestamps by taking a snapshot of an internal counter.
+@item Reading out the fine part from the Acam.
+@item Merging these values together, aligning the result to the local timebase and outputting everything in a format digestible by the pulse generators.
 @end itemize

 @subsection Timestamp format

 The FD core uses standard White Rabbit timestamp format (@ref{fig:ts_format}), where each timestamp consists of 3 fields:
 @itemize
-@item 40 bit @code{seconds}: number of TAI seconds since 1st January, 1970,
+@item 40 bit @code{seconds}: number of TAI seconds since 01.01.1970 (Unix epoch).
 @item 28-bit @code{coarse}: number of reference clock cycles since the beginning of current second. In case of the FD, reference clock is 125 MHz, so @code{coarse} range is 0 to 124999999.
 @item 12-bit @code{frac}: fraction of 8 ns, scaled to span full 12 bit range. @code{frac = 4095} @code{8 ns * 4095/4096}.
 @end itemize
@@ -507,19 +522,19 @@ For example, a hardware timestamp of @code{12:50000:1000} is 12 seconds + (50000
 @subsection TDC timing

 Before we time tag any pulses, we need to make sure the TDC is referenced to something and the time shift between 
-this something and the ACAM's internal time base is known (or even better, constant). Inside the TDC core, the time base consists of:
+this something and the Acam's internal time base is known (or even better, constant). Inside the TDC core, the time base consists of:
 @itemize
-@item @code{utc_count} - seconds counter,
-@item @code{coarse_count} - coarse start cycle counter incremented after each TDC start event. In our case, the TDC start period of 256 ns is achieved by driving the Start input with a 7.8125 MHz clock coming from the PLL and gating out every second cycle via ACAM's StartDis input to effectively divide it by 2.
-@item @code{start_count} - start subcycle counter (0..31), reset at start event,
-@item @code{timebase_offset} - offset between the ACAM's and core's internal timescales.
+@item @code{utc_count}: seconds counter.
+@item @code{coarse_count}: coarse start cycle counter incremented after each TDC start event. In our case, the TDC start period of 256 ns is achieved by driving the Start input with a 7.8125 MHz clock coming from the PLL and gating out every second cycle via Acam's StartDis input to effectively divide it by 2.
+@item @code{start_count}: start subcycle counter (0..31), reset at start event.
+@item @code{timebase_offset}: offset between the Acam's and core's internal timescales.
 @end itemize

-A snapshot of these counters is sampled for every input event. The values are later merged with the fine part read from the ACAM TDC to obtain the final, White Rabbit-formatted timestamp.
+A snapshot of these counters is sampled for every input event. The values are later merged with the fine part read from the Acam TDC to obtain the final, White Rabbit-formatted timestamp.

 The interesting thing is how the TDC timebase is related to the external time scale, as TDC start events occur at fixed multiplies of 256 ns, but a PPS pulse (@code{csync_p1_i}) from the counter sync 
-unit can come anytime (with 8 ns granularity). The most straightformward way would be to align the TDC start
-pulse with the PPS pulse - it wouldn't be safe though, as it would require using the AD9516's output divider align feature, which is asynchronous.
+unit can come anytime (with 8 ns granularity). The most straightforward way would be to align the TDC start
+pulse with the PPS pulse by resetting the output dividers in the AD9516. This solution wouldn't be very safe though, as the PLL clock before division is 750 MHz. Ensuring correct setup/hold times between the FPGA output pin and the counter synchronization input in the PLL at such frequency is very difficult.
 The TDC core employs a simple trick here: when a resync pulse comes, it stores the difference between the lowest 
 bits of the @code{csync_coarse} counter and the start subcycle counter (@code{timebase_offset} signal in @code{p_start_subcycle_counter} process). This difference is added to the timestamps at the postprocessing stage to compensate for time base shift. See @ref{fig:tdc_timebase} for a graphical explanation.

@@ -530,7 +545,7 @@ bits of the @code{csync_coarse} counter and the start subcycle counter (@code{ti

 @subsection Input stage and TDC control

-This part of the core takes care of the coarse input pulse and TDC start/stop enable singnals. It is responsible for:
+This part of the core takes care of the coarse input pulse and TDC start/stop enable signals. It is responsible for:

 @itemize
 @item @b{Sampling coarse pulse input.}
@@ -545,9 +560,9 @@ input pulses come too close to each other or in case of poor quality or noise on
 and @code{p_gen_acam_stop} drive the TDC's START and STOP disable signals. The former ensures that the start 
 input is not enabled in the middle of a rising edge of the 7.125 MHz start clock and gates the StartDis TDC input to effectively divide the start clock by 2. The latter enables the stop input when the TDC has received at least one correct start pulse.

-@item @b{Rejecting pulses that do not meet the requirements}. In our case - shorter than 24 ns or containing glitches. Width detection is done in the main state machine (@code{p_main_fsm}) by shifting in subsequent samples into a register (@code{width_check_sreg}) and checking if the register contains only ones. Glitch detection exploits sensitivity of ACAM's Stop input: since we disable the trigger input right after we have detected a rising edge, the ACAM shall normally produce only one timestamp. Therefore, if the FIFO does not become empty immediately after read, a spurious pulse must have been tagged. Such situation may occur when the board is fed with a train of densely spaced pulses (where the shift register doesn't notice the gaps between them, but the ACAM does). If any glitch or incorrect pulse is detected, the timestamp is ignored, and the ACAM is reset by asserting @code{AluTrigger} line.
+@item @b{Rejecting pulses that do not meet the requirements}. In our case - shorter than 24 ns or containing glitches. Width detection is done in the main state machine (@code{p_main_fsm}) by shifting in subsequent samples into a register (@code{width_check_sreg}) and checking if the register contains only ones. Glitch detection exploits sensitivity of Acam's Stop input: since we disable the trigger input right after we have detected a rising edge, the Acam shall normally produce only one timestamp. Therefore, if the FIFO does not become empty immediately after read, a spurious pulse must have been tagged. Such situation may occur when the board is fed with a train of densely spaced pulses (where the shift register doesn't notice the gaps between them, but the Acam does). If any glitch or incorrect pulse is detected, the timestamp is ignored, and the Acam is reset by asserting @code{AluTrigger} line.

-@item @b{Reading out the ACAM FIFO}, done by the main state machine. After detecting a rising edge on the coarse pulse input, the FSM waits for the timestamp to appear in ACAM's FIFO and reads it out from register @code{8}. Several wait states are introduced by the FSM to ensure the read sequence does not cause setup/hold violations or SI problems. The fine value is passed along with the coarse counters and offsets to the postprocessing unit.
+@item @b{Reading out the Acam FIFO}, done by the main state machine. After detecting a rising edge on the coarse pulse input, the FSM waits for the timestamp to appear in Acam's FIFO and reads it out from register @code{8}. Several wait states are introduced by the FSM to ensure the read sequence does not cause setup/hold violations or signal integrity (SI) problems. The fine value is passed along with the coarse counters and offsets to the postprocessing unit.

 @end itemize

@@ -555,14 +570,14 @@ input is not enabled in the middle of a rising edge of the 7.125 MHz start clock

 @node{Timestamp postprocessing}

-The postprocessor combines the fine value read from the ACAM with the coarse value captured using a counter into a WR-compatible timestamp and aligns it to selected time base. Postprocessing is done in the @code{p_postprocess_tags} process. It consists of 4 pipelined stages:
+The postprocessor combines the fine value read from the Acam with the coarse value captured using a counter into a WR-compatible timestamp and aligns it to selected time base. Postprocessing is done in the @code{p_postprocess_tags} process. It consists of 4 pipelined stages:
 @itemize

-@item Subtract the start offset value from the fine part. ACAM's ALU can't handle negative numbers, therefore each timestamp is internally adjusted by a value defined in the @code{StartOff[1,2]} ACAM's control registers. This step subtracts this value (programmable via @code{ASOR} register, so that a pulse that occured in phase with a start pulse gets a fine value near to 0. Some timestamps may have negative fine values after start offsest subtraction. This results from the internal ACAM's delays - sometimes it may reference a stop event to a start event 
+@item Subtract the start offset value from the fine part. Acam's ALU can't handle negative numbers, therefore each timestamp is internally adjusted by a value defined in the @code{StartOff[1,2]} Acam's control registers. This step subtracts this value (programmable via @code{ASOR} register, so that a pulse that occured in phase with a start pulse gets a fine value near to 0. Some timestamps may have negative fine values after start offsest subtraction. This results from the internal Acam's delays - sometimes it may reference a stop event to a start event 
 that occured afterwards. The range of fine values is therefore wider than the start period - an event occuring 250 ns after a start pulse can be either timestamped as 250 or -6 ns. 

-@item Rescale the fine value from ACAM (expressed as a number of 41 ps bins) to WR time format (where 1 ps = 8 ns / 4096). This is done by simply multiplying by a constant scalefactor (programmable via @code{ADSFR} register).
-@item Check consistency between the coarse counter @code{coarse_count} and the fine part. In ideal case, the final timestamp should be a simple sum of @code{coarse_count} * 256 ns and the fine part. In @i{The Real World}, transitions of the fine value (i.e. 256 ns to 0 ns) in the ACAM are not consistent with transitions of the coarse counter in the FPGA. ACAM's internal start is shifted forward with respect to the FPGA's start signal. In certain cases, the fine part may have already flipped the 256 ns boundary, while the coarse counter has not counted up yet, producing a timestamp with an error of 256 ns (see @ref{fig:tdc_merge}). Also, big fine values at the the end of the range may be interleaved with negative ones, depending on ACAM's mood.
+@item Rescale the fine value from Acam (expressed as a number of 41 ps bins) to WR time format (where 1 ps = 8 ns / 4096). This is done by simply multiplying by a constant scalefactor (programmable via the @code{ADSFR} register).
+@item Check consistency between the coarse counter @code{coarse_count} and the fine part. In ideal case, the final timestamp should be a simple sum of @code{coarse_count} * 256 ns and the fine part. In @i{The Real World}, transitions of the fine value (i.e. 256 ns to 0 ns) in the Acam are not consistent with transitions of the coarse counter in the FPGA. Acam's internal start is shifted forward with respect to the FPGA's start signal. In certain cases, the fine part may have already flipped the 256 ns boundary, while the coarse counter has not counted up yet, producing a timestamp with an error of 256 ns (see @ref{fig:tdc_merge}). Also, big fine values at the the end of the range may be interleaved with negative ones, depending on Acam's mood.

 The postprocessor mitigates this problem by using the @code{start_count} counter. If @code{start_count} value is low (indicating that we are close to the beginning of an FPGA start cycle), while the fine part is high (meaning that the TDC has not yet noticed the ``fresh'' start pulse), the timestamp's @code{coarse_count} need to be adjusted by subtracting one start period. Thresholds for the comparisons are programmable via @code{ATMCR} register, their values were obtained experimentally.

@@ -575,46 +590,46 @@ The postprocessor mitigates this problem by using the @code{start_count} counter
 @caption{Relations between coarse and fine timestamp parts.}
 @end float

-As a result, we get a WR-formatted timestamp, with constant systematic error. This error is hardware-specific and is compensated in software by adding an offset to all timestamps read from the card and all programmed delay values. The offset value is determined individually for each mezzanine during factory or DDMTD calibration and written in the calibration EEPROM.
+As a result, we get a WR-formatted timestamp, which may have a constant offset with respect to the WR/local timescale. This offset results from PCB trace lengths, component properties and the choice of the postprocessing register values and is compensated in software by adding a correction to all timestamps read from the card and all programmed delay values. The correction value is determined individually for each mezzanine during factory or DDMTD calibration and written in the calibration EEPROM. Typical value is 127.5 ns.

 Note that the postprocessor can be disabled for debugging purposes by setting @code{TSBCR.RAW} bit. In such case, raw counter and fine values are written to the buffer instead of the final timestamp. This feature is used in production tests.

 @subsection Statistics unit

-The ACAM core includes a statistics unit. Its purpose is to collect data that may be helpful in debugging and performance tuning of the core:
+The Acam core includes a statistics unit. Its purpose is to collect data that may be helpful in debugging and performance tuning of the core:
 @itemize
-@item count all detected input pulses,
-@item count pulses that have been correctly tagged,
-@item measure worst-case input-to-timestamp latency (which is important for delay applications as it defines minimum safe delay value). In case of the ACAM configured in G-Mode, the latency is 360 ns. 
+@item Count all detected input pulses.
+@item Count pulses that have been correctly tagged.
+@item Measure worst-case input-to-timestamp latency (which is important for delay applications as it defines minimum safe delay value). In case of the Acam configured in G-Mode, the latency is 360 ns. 
 @end itemize

-@subsection ACAM host interface
+@subsection Acam host interface

-The main TDC state machine lets the host directly access ACAM's control registers. Host (a.k.a. bypass) mode is active when @code{GCR.BYPASS} bit is set. The ACAM must be programmed for G-mode operation prior to enabling the hardware readout. In order to write a single ACAM register follow the procedure below:
+The main TDC state machine lets the host directly access Acam's control registers. Host (a.k.a. bypass) mode is active when @code{GCR.BYPASS} bit is set. The Acam must be programmed for G-mode operation prior to enabling the hardware readout. In order to write a single Acam register follow the procedure below:
 @itemize
-@item set the address of the ACAM register by programming the GPIO expander,
-@item write the desired word to @code{TDR} register,
-@item write 1 to @code{TDCSR.WRITE} bit. 
-@item wait at least 1 microsecond before commencing another write.
+@item Set the address of the Acam register by programming the GPIO expander.
+@item Write the desired word to @code{TDR} register.
+@item Write 1 to @code{TDCSR.WRITE} bit.
+@item Wait at least 1 microsecond before commencing another write.
 @end itemize
 Read procedure is quite similar:
 @itemize
-@item set the address of the ACAM register by programming the GPIO expander,
-@item write 1 to @code{TDCSR.READ} bit. 
-@item wait at least 1 microsecond.
-@item read the value returned by ACAM from @code{TDR} register.
+@item Set the address of the Acam register by programming the GPIO expander.
+@item Write 1 to @code{TDCSR.READ} bit. 
+@item Wait at least 1 microsecond.
+@item Read the value returned by Acam from @code{TDR} register.
 @end itemize
-Note that once the TDC is programmed, its address (via the SPI expander) must be set to @code{8} (ACAM FIFO1 register), so that the FSM can read correct data from the right FIFO register.
+Note that once the TDC is programmed, its address (via the SPI expander) must be set to @code{8} (Acam FIFO1 register), so that the FSM can read correct data from the right FIFO register.

 @subsection Host timestamp readout
 Relevant files: @code{fd_ts_buffer.vhd}.

-The FD provides the values of all input and output timestamps through a 1024-entry ring buffer. Each timestamp is associated with a sequence number and the source channel identifier. Timestamp readout can be enabled anytime and for any mode of operation (delay/TDC/pulse generator). Readout procedure goes as follows:
+The FD provides the values of all input and output timestamps through a 1024-entry ring buffer. Each timestamp is associated with a sequence number and the source channel identifier. Timestamp readout can be enabled anytime and for any mode of operation (delay/TDC/pulse generator). The readout procedure goes as follows:
 @itemize
-@item set channels we are interested in reading from in @code{TSBCR.CHAN_MASK}. Enable readout by setting @code{TSBCR.ENABLE}.
-@item poll the buffer by reading @code{TSBCR.EMPTY} bit or by handling the TS buffer interrupt. Do not attempt both ways simultaneously.
-@item read the timestamp from @code{TSBR} registers. Order doesn't matter.
-@item release the timestamp from the buffer and proceed to the next one by writing anything to @code{TSBR_ADVANCE} register.
+@item Set channels we are interested in reading from in @code{TSBCR.CHAN_MASK}. Enable readout by setting @code{TSBCR.ENABLE}.
+@item Poll the buffer by reading @code{TSBCR.EMPTY} bit or by handling the TS buffer interrupt. Do not attempt both ways simultaneously.
+@item Read the timestamp from @code{TSBR} registers. Order doesn't matter.
+@item Release the timestamp from the buffer and proceed to the next one by writing anything to the @code{TSBR_ADVANCE} register.
 @end itemize

 In case of an overflow, the oldest timestamps in the buffer are subsequently replaced by the most recent ones. Loss of timestamps due to overflow can be detected by comparing the sequence numbers. If the buffer is handled through interrupts, coalescing mechanism is provided to reduce CPU load for larger amounts of timestamps. See @code{TSBIR} register description for details.
@@ -630,10 +645,10 @@ An output stage produces one or more pulses of given width and spacing starting
 @caption{Output stage VHDL overview.}
 @end float

-The structure of the output stage VHDL is shown in @ref{fig:vhdl_output_stage}. The datapath consists of two accumulateing timestamp adders that calculate start- and end-of-pulse timestamps. The adders' outputs are compared with the time base counter, resulting with pulse start/end strobe signals. The timing of output pulses is defined by 3 sets of registers:
+The structure of the output stage VHDL is shown in @ref{fig:vhdl_output_stage}. The datapath consists of two accumulateing timestamp adders that calculate start- and end-of-pulse timestamps. The adders' outputs are compared with the time base counter, resulting in pulse start/end strobe signals. The timing of output pulses is defined by 3 sets of registers:
 @itemize
-@item @code{start}: delay between TDC timestamp and the rising edge of the output pulse (delay mode) or absolute time of the rising edge of the output pulse (pulse generator mode),
-@item @code{end}: same for the falling edge,
+@item @code{start}: delay between TDC timestamp and the rising edge of the output pulse (delay mode) or absolute time of the rising edge of the output pulse (pulse generator mode).
+@item @code{end}: same for the falling edge.
 @item @code{delta}: delay between subsequent output pulses.
 @end itemize
 Multiplexers are used to configure the data path for a given output mode. Comparators and adders drives a simple, sequential state machine, which:
@@ -642,15 +657,16 @@ Multiplexers are used to configure the data path for a given output mode. Compar
 @item Takes the fractional part of the rising edge output timestamp, multiplies it by the calibration factor @code{FRR} and sends it to the delay line for a given channel,
 @item Waits until the arbiter updates the delay line with the new fractional value,
 @item Waits for the start comparator hit and asserts coarse output high,
-@item Repeats points 2...4 for the falling edge.
+@item Repeats points 2...4 for the falling edge,
 @item Checks if we want more than one pulse - if true, it adds @code{delta} value to the start/end timestamp and goes to point 2. If not, it goes idle.
 @end enumerate

-Access to the delay lines is multiplexed by a round-robin arbiter (@code{fd_delay_line_arbiter}). Worst-case update latency is 4 * 32 ns = 128 ns, imposing a width/spacing limit of 200 ns. Shorter/denser pulses (up to 50 ns) can be still produced by setting @code{DCR.NO_FINE} bit, width widhts/spacing values restricted to multiplies of 4 ns. Given the TDC latency of 360 ns + few clock cycles taken by pipelining, the minimum safe delay setting is therefore 600 ns.
+Access to the delay lines is multiplexed by a round-robin arbiter (@code{fd_delay_line_arbiter}). Worst-case update latency is 4 * 32 ns = 128 ns, imposing a width/spacing limit of 200 ns. Shorter/denser pulses (up to 50 ns) can be still produced by setting @code{DCR.NO_FINE} bit, with width/spacing values being restricted to multiplies of 4 ns. Given the TDC latency of 360 ns and a few clock cycles taken by pipelining, the minimum safe delay setting is therefore 600 ns.

+@page
 @subsection Programming the output stage
 @itemize
-@item Set the mode in @code{DCR.MODE} bit
+@item Set the mode in @code{DCR.MODE} bit.
 @item Set the absolute start time or delay and pulse spacing in @code{DCR.x_START}, @code{DCR.x_END} and @code{DCR.x_DELTA} registers.
 @item Acknowledge the changes by writing @code{DCR.UPDATE} bit.
 @item If the output is not already enabled, write @code{DCR.ENABLE} bit and enable the corresponding SSR switch through the SPI GPIO.
@@ -658,8 +674,8 @@ Access to the delay lines is multiplexed by a round-robin arbiter (@code{fd_dela

 @subsection Other important things
 @itemize
-@item The design is highly pipelined to meet timing for a 125 MHz clock with rather wide datapath (40 + 28 + 12 = 80 bit add/compare operations).
-@item Start/end/delta and mode selection registers are shadowed to ensure atomic updates of output pulse timings. 
+@item The design is highly pipelined to meet timing for a 125 MHz clock with a rather wide datapath (40 + 28 + 12 = 80 bit add/compare operations).
+@item Start/end/delta and mode selection registers are shadowed to ensure atomic updates of output pulse timings. By shadowing we mean that there are each of these registers has an internal copy that is used by the output logic. All copies are updated simultaneously when @code{DCR.UPDATE} bit is written.
 @item Offset resulting from pipelining and data path delays is systematic and must be compensated by adjusting the start/end values in the software.
 @item Checking if the output has triggered can be done by polling @code{DCR.PG_TRIG} bit.
 @item @code{FRR} register must be initialized with correct calibration coefficient (see @ref{Output stage calibration}).
@@ -669,27 +685,28 @@ Access to the delay lines is multiplexed by a round-robin arbiter (@code{fd_dela

 @subsection OneWire

-The FD core incorporates a dedicated Dallas's 1-Wire bus master core for accessing the temperature sensor/ID chip from a non-deterministic Linux CPU (1-Wire requires tight timing to operate correctly). The core's documentation is available at the Opencores project page (@xref{References}).
+The FD core incorporates a dedicated Dallas's 1-Wire bus master core for accessing the temperature sensor/ID chip from a non-deterministic host (1-Wire requires tight timing to operate correctly). The core's documentation is available at the Opencores project page [6].

 @subsection I2C

-There is also a simple bit-banged I2C master for talking with the I2C EEPROM, accessible through @code{I2CR} register. The driver uses it for retreiving calibration data and identification of the mezzanine.
+There is also a simple bit-banged I2C master for talking with the I2C EEPROM, accessible through the @code{I2CR} register. The driver uses it for retreiving calibration data and identification of the mezzanine.

 @subsection SPI Master

-It is a specialized core (not a general-purpose Wishbone SPI master), accessible via @code{SCR} register and interfacing with all SPI peripherals (VCXO DAC, GPIO and AD9516). Special features include:
+The SPI Master is a specialized core (not a general-purpose Wishbone SPI master), accessible via the @code{SCR} register and interfacing with all SPI peripherals (VCXO DAC, GPIO and AD9516). Special features include:
 @itemize
-@item two concurrent, arbitrated write ports: software via @code{SCR} register and hardware via @code{tm_dac_value} port
-@item hardware port takes priority over software access and lets the SoftPLL update the VCXO DAC in a deterministic way, regardless of driver's accesses to the GPIO and PLL chips.
-@item atomic read/write access thanks to a single control/status/data register.
+@item Two concurrent, arbitrated write ports: software via @code{SCR} register and hardware via @code{tm_dac_value} port.
+@item The hardware port takes priority over software access and lets the SoftPLL update the VCXO DAC in a deterministic way, regardless of driver's accesses to the GPIO and PLL chips.
+@item Atomic read/write access thanks to a single control/status/data register.
 @end itemize

+@page
 @subsection Testing logic

 There are two extra cores used during production testing and characterization of the card:
 @itemize
-@item a PWM driver, accessible via @code{TDER2} register. Used in lab tests for driving a Peltier module in order to characterize the temperature effects on the mezzanine.
-@item a frequency meter (register @code{TDER1}), measuring the mezzanine's VCXO frequency against the carrier's system clock. Used to characterize the tuning range of the oscillator during production test.
+@item A PWM driver, accessible via the @code{TDER2} register. Used in lab tests for driving a Peltier module in order to characterize the temperature effects on the mezzanine.
+@item A frequency meter (@code{TDER1}), measuring the mezzanine's VCXO frequency against the carrier's system clock. Used to characterize the tuning range of the oscillator during production test.
 @end itemize

 @section Initializing the card
@@ -698,7 +715,7 @@ Since initialization of the FD mezzanine is not simple and straightforward, a br
 @enumerate
 @item Check for presence of the FD core by verifying @code{IDR} register.
 @item Check mezzanine presence through @code{GCR.FMC_PRESENT} bit.
-@item Read calibration EEPROM via the I2C master. Parse and verify its contents.
+@item Read the calibration EEPROM via the I2C master. Parse and verify its contents.
 @item Reset the mezzanine via @code{RSTR} register. Hold the FD core (except SPI & I2C) in reset.
 @item Program the AD9516 PLL. Use register values included with the driver/test program code.
 @item Initialize 1-wire temperature sensor. Read card serial number and temperature.
@@ -715,13 +732,14 @@ provided in the test program.
 @end enumerate


-Now the card should be ready for timestamp readout and output programming. For code examples please look at @code{fdelay_lib.c} file in the test program.
+Now the card should be ready for timestamp readout and output programming. For code examples please look at @code{fdelay_lib.c} file in the test program [3].

+@page
 @section Carrier implementation example

 Relevant files: @code{svec_top.vhd}.

-An example FD VHDL core implementation on a SVEC FMC carrier (@xref{References}) is shown in @ref{fig:svec_top_block}.
+An example FD VHDL core implementation on a SVEC FMC carrier [8] is shown in @ref{fig:svec_top_block}.

 @float Figure,fig:svec_top_block
 @center @image{drawings/svec_top_block, 16cm,,,.pdf}
@@ -750,22 +768,25 @@ For more details, refer to the source files and comments inside.

 @node{Output stage calibration}

-The role of this calibration mechanism is to ensure linearity of the output stages. FDs output pulses are generated by a coarse counter (with 8 ns granularity) that is further delayed by an SY99295 chip. The timestamp of the output pulse is therefore equal to:
+The role of this calibration mechanism is to make sure the SY89295 fine delay lines introduce delays consistent with the programmed settings. In @i{The Ideal World}, the tap size of a SY89295 is 10 ps, so programming the chip to 800 shall result with a delay of 8 ns. In reality, the tap size depends on PVT effects - we observed that some chips, when set to 800 taps produce 7.5 ns or 8.5 ns instead of the requested 8 ns.  
+As mentioned earlier, the FD output stage works by producing an 8 ns resolution coarse pulse with a counter and adjusting it precisely in an SY99295 chip, according to the equation:

-@code{t_actual = floor(t_out / 8ns) + alpha * (t_out mod 8ns)}
+@code{t_measured = floor(t_out / 8ns) + FRR * (t_out mod 8ns)}


-where @code{t_actual} is the measured timestamp, and @code{t_out} is the requested one. The @code{alpha} parameter relates the fractional part with the number of fine delay line taps required to produce it. In @i{The Ideal World}, it should be 100 taps/ns, as the typical tap size of SY89259 is 10 ps. 
+where @code{t_measured} is the measured timestamp of the output pulse, and @code{t_out} is the one the output stage was requested to produce. The @code{FRR} parameter relates the fractional (modulo) part of the timestamp with the number of fine delay line taps required to accurately reproduce it. In @i{The Ideal World}, it should be 100 taps/ns. If the alpha value is wrong, output pulses will be imprecise. To make things worse, the error will not be proportional to the requested delay, but only to its modulo part. Therefore, pulses whose timestamps have small fractional value (for example, 1000 ns mod 8 ns = 0) will have no error at all, while other ones (e.g. 1007.9 ns) will have an error of as much as 1 ns. 

-In reality, tap size depends on PVT effects and can cause severe nonlinearity in output stage response, illustrated in @ref{fig:calib_why}. For example, when the core requests a fine adjustment of 8 ns, and the actual one is 7 ns, output pulses will exhibit non-gaussian jitter of 1 ns , which is far too high to meet the design specifications. Process-specific drifts of 1 ns have been observed for SY89295 chips used in our production cards. Therefore, we need to calibrate the @i{alpha} value for each SY89295. This is done everytime the card starts up.
+Since there is absolutely no corellation between the pulses coming to the TDC and the card's reference clock, fractional parts of the input timestamps and the values written to the SY89295 for each output pulse look purely random. Therefore, one pulse may have an error of 0, while the next one might be off by almost a nanosecond - an effect that in technical terms is called huge, non-gaussian jitter, exceeding by far the 100 ps specification requirement.

 @float Figure,fig:calib_why
-@center @image{drawings/calib_why, 10cm,,,.pdf}
+@center @image{drawings/calib_why, 15.5cm,,,.pdf}
 @caption{Effects of uncalibrated output delay line.}
 @end float

+Fortunately, this effect is mitigated by calibrating the @i{FRR} value for each SY89295 delay line. This is done every time the card starts up.
+
 The output stage calibration mechanism is depicted in @ref{fig:calib_output}. It works by feeding the output stage with 
-calibration pulses and measuring the in-out delay of '89295 delays for different tap settings in order to find a point at which they
+calibration pulses and measuring the in-out delay of SY89295 delays for different tap settings in order to find a point at which they
 delay the signal by exactly 8 ns more than at tap setting of 0. The TDC, reconfigured in the I-mode (single ended start input and
 4 single ended stop inputs, one per output) is reused as a calibrator (thanks to its' voltage adjusting PLL, we know that its definition of 8 ns
 is not worse than of the reference oscillator). Precision better than 10 ps rms (single tap) is achieved by averaging multiple measurements.
@@ -786,15 +807,16 @@ the output stage scale factor without disturbing the outputs with extra calibrat

 The same method (with full range sweeping instead of divide-and-conquer) is used to measure linearity (INL/DNL) of the delay lines during production test.

+@page
 @section DDMTD I/O delay calibration

 Careful readers may have noticed that the previous calibration process only minimizes jitter. The purpose of DDMTD calibration is to measure 
 the end-to-end delay of an (almost) entire mezzanine. @ref{fig:ddmtd_calibration} shows the calibration components:
 @itemize
-@item input of the TDC is fed with a square waveform of @code{clk_ref_0} / 144, simulating real input pulses with the fastest allowed frequency (to speed up measurements and increase resolution) and some safety margin.
-@item delay path is programmed to a minimum insertion delay of 600 ns. 
-@item input and output pulses are sampled by another clock with two identical flip flops. Frequency of the samling clock is slightly offset with respect to 
-@code{clk_ref_0} / 144 (in our case the offset is 1/16384). Flip flop outputs are hence downconverted versions of the in/out pulses and keep their timing relations, but
+@item The input of the TDC is fed with a square waveform of @code{clk_ref_0} / 144, simulating real input pulses with the fastest allowed frequency (to speed up measurements and increase resolution) and some safety margin.
+@item The delay path is programmed to a minimum insertion delay of 600 ns. 
+@item Input and output pulses are sampled by another clock with two identical flip flops. Frequency of the samling clock is slightly offset with respect to 
+@code{clk_ref_0} / 144 (in our case the offset is 1/16384). The flip flop outputs are hence downconverted versions of the in/out pulses and keep their timing relations, but
 scaled down by a factor of 16384, so a delay of 10 picoseconds is seen as 16.384 ns. This is very easy to measure using a simple counter.
 @end itemize

@@ -805,13 +827,13 @@ scaled down by a factor of 16384, so a delay of 10 picoseconds is seen as 16.384

 Since the offset clock is produced by the PLL in the White Rabbit core, DDMTD calibration
 is possible only with WR-enabled carriers. It is not done by default in the driver, but
-can be run using @code{ddmtd_calibration} tool from the @code{software/tests/} subdirectory in the repo. 
+can be run using @code{ddmtd_calibration} tool from the @code{software/tests/} subdirectory in the repo [3]. 

 Note that this method is still not ideal - it is prone to PVT differences between the calibration flip flops and it does not take into account the delays introduced by
 the output cutoff and input selection switches. Therefore, production tests involve calibration with an external time interval meter. Tests performed on a batch of 80 cards
-have shown that the error between DDMTD calibration mechanism and the external TIM did not exceed 800 ps.
+have shown that the error between DDMTD calibration mechanism and the external time interval meter did not exceed 800 ps.

-More information on DDMTD phase/time measurement techniques is available in Tom's MSc thesis (@xref{References}).
+More information on DDMTD phase/time measurement techniques is available in Tom's MSc thesis [2].


 @page
@@ -851,25 +873,21 @@ The output stage register block controls a single FD output stage.
 @chapter References
 @node{References}

-@itemize
+@enumerate
 @item Official schematics and PCB design (CERN EDMS)

-@url{https://edms.cern.ch/nav/EDA-02267-V5-1}
+@url{https://edms.cern.ch/nav/EDA-02267-V5-2}
 @item Tom's MSc thesis (a bible of White Rabbit timing)

 @url{http://www.ohwr.org/documents/80}
-
 @item Hardware homepage & Wiki

 @url{http://www.ohwr.org/projects/fmc-delay-1ns-8cha}
-@item Linux device driver project
-
-@url{http://www.ohwr.org/projects/fine-delay-sw}
 @item Official user's manual

 @url{http://www.ohwr.org/documents/179}

-@item ACAM TDC-GPX datasheet
+@item Acam TDC-GPX datasheet

 @url{http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf‎}

@@ -892,6 +910,14 @@ The output stage register block controls a single FD output stage.

 @url{http://www.ohwr.org/projects/pts}

-@end itemize
+@item Analog Devices PLL design software (@i{AdiSimClk})
+
+@url{http://www.analog.com/en/rf-tools/adisimclk/topic.html}
+
+@item @code{wbgen2} - a Wishbone slave generator
+
+@url{http://www.ohwr.org/projects/wishbone-gen}
+
+@end enumerate

 @bye