Commit eca0894f authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing

parent 84dca3f5
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-11-26
-- Last update: 2018-08-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -229,14 +229,14 @@ begin -- behavioral
end if;
end process;
U_Sync_WR_Csync : gc_pulse_synchronizer
U_Sync_WR_Csync : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
d_p_i => csync_wr_sysclk,
q_p_o => csync_wr_refclk);
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys_i,
clk_out_i => clk_ref_i,
rst_out_n_i => rst_n_ref_i,
d_p_i => csync_wr_sysclk,
q_p_o => csync_wr_refclk);
tmo_restart <= wr_state_changed;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-22
-- Last update: 2018-08-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -176,16 +176,17 @@ begin -- behavioral
fifo_write <= not fifo_full and tag_valid_i;
U_Clock_Adjustment_Fifo : generic_async_fifo
U_Clock_Adjustment_Fifo : generic_async_fifo_dual_rst
generic map (
g_data_width => fifo_in'length,
g_size => c_FIFO_SIZE)
port map (
rst_n_i => rst_n_sys_i,
rst_wr_n_i => rst_n_ref_i,
clk_wr_i => clk_ref_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
rst_rd_n_i => rst_n_sys_i,
clk_rd_i => clk_sys_i,
q_o => fifo_out,
rd_i => fifo_read,
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2018-08-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -552,13 +552,14 @@ begin -- rtl
gen_with_direct_io_tdc : if(g_with_direct_timestamp_io) generate
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_0_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_sys,
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
clk_in_i => clk_ref_0_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys,
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
process(clk_ref_0_i)
begin
......@@ -630,14 +631,14 @@ begin -- rtl
gen_with_direct_io : if g_with_direct_timestamp_io generate
U_Sync_Valid_Pulse : gc_pulse_synchronizer
U_Sync_Valid_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_ref_0_i,
rst_n_i => rst_n_ref,
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys,
clk_out_i => clk_ref_0_i,
rst_out_n_i => rst_n_ref,
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
process(clk_sys_i)
begin
......
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