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FMC DEL 1ns 4cha
Commit eca0894f authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing

parent 84dca3f5
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Showing with 27 additions and 25 deletions
hdl/rtl/fd_csync_generator.vhd
View file @ eca0894f
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-11-26 -- Last update: 2018-08-03
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -229,14 +229,14 @@ begin -- behavioral ...@@ -229,14 +229,14 @@ begin -- behavioral
end if; end if;
end process; end process;
U_Sync_WR_Csync : gc_pulse_synchronizer U_Sync_WR_Csync : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, rst_in_n_i => rst_n_sys_i,
rst_n_i => rst_n_ref_i, clk_out_i => clk_ref_i,
d_p_i => csync_wr_sysclk, rst_out_n_i => rst_n_ref_i,
q_p_o => csync_wr_refclk); d_p_i => csync_wr_sysclk,
q_p_o => csync_wr_refclk);
tmo_restart <= wr_state_changed; tmo_restart <= wr_state_changed;
......
hdl/rtl/fd_ring_buffer.vhd
View file @ eca0894f
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-05-22 -- Last update: 2018-08-02
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -176,16 +176,17 @@ begin -- behavioral ...@@ -176,16 +176,17 @@ begin -- behavioral
fifo_write <= not fifo_full and tag_valid_i; fifo_write <= not fifo_full and tag_valid_i;
U_Clock_Adjustment_Fifo : generic_async_fifo U_Clock_Adjustment_Fifo : generic_async_fifo_dual_rst
generic map ( generic map (
g_data_width => fifo_in'length, g_data_width => fifo_in'length,
g_size => c_FIFO_SIZE) g_size => c_FIFO_SIZE)
port map ( port map (
rst_n_i => rst_n_sys_i, rst_wr_n_i => rst_n_ref_i,
clk_wr_i => clk_ref_i, clk_wr_i => clk_ref_i,
d_i => fifo_in, d_i => fifo_in,
we_i => fifo_write, we_i => fifo_write,
wr_full_o => fifo_full, wr_full_o => fifo_full,
rst_rd_n_i => rst_n_sys_i,
clk_rd_i => clk_sys_i, clk_rd_i => clk_sys_i,
q_o => fifo_out, q_o => fifo_out,
rd_i => fifo_read, rd_i => fifo_read,
......
hdl/rtl/fine_delay_core.vhd
View file @ eca0894f
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2014-03-24 -- Last update: 2018-08-03
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -552,13 +552,14 @@ begin -- rtl ...@@ -552,13 +552,14 @@ begin -- rtl
gen_with_direct_io_tdc : if(g_with_direct_timestamp_io) generate gen_with_direct_io_tdc : if(g_with_direct_timestamp_io) generate
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer U_Sync_TDC_Valid_Out : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_ref_0_i, clk_in_i => clk_ref_0_i,
clk_out_i => clk_sys_i, rst_in_n_i => rst_n_ref,
rst_n_i => rst_n_sys, clk_out_i => clk_sys_i,
d_p_i => tag_valid, rst_out_n_i => rst_n_sys,
q_p_o => tdc_valid_o); d_p_i => tag_valid,
q_p_o => tdc_valid_o);
process(clk_ref_0_i) process(clk_ref_0_i)
begin begin
...@@ -630,14 +631,14 @@ begin -- rtl ...@@ -630,14 +631,14 @@ begin -- rtl
gen_with_direct_io : if g_with_direct_timestamp_io generate gen_with_direct_io : if g_with_direct_timestamp_io generate
U_Sync_Valid_Pulse : gc_pulse_synchronizer2
U_Sync_Valid_Pulse : gc_pulse_synchronizer
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_0_i, rst_in_n_i => rst_n_sys,
rst_n_i => rst_n_ref, clk_out_i => clk_ref_0_i,
d_p_i => outx_valid_i(i), rst_out_n_i => rst_n_ref,
q_p_o => channels(i).tag.valid); d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
process(clk_sys_i) process(clk_sys_i)
begin begin
......
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