Commit f5f3da02 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/rtl: fix unclear timebase offset signal name

parent 4e9db31d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2013-02-06
-- Last update: 2013-07-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -75,7 +75,7 @@ entity fd_acam_timestamp_postprocessor is
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
acam_timebase_offset_i : in std_logic_vector(5 downto 0);
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
......@@ -195,7 +195,7 @@ begin -- behavioral
-- 16 at the AD9516 PLL). So, every time there's a counter resync event
-- (from associated WR PTP Core or an internal one), we simply count
-- the number of ref clock cycles between the 1-PPS and the nearest TDC
-- start edge and store it in acam_subcycle_offset_i.
-- start edge and store it in acam_timebase_offset_i.
--
-- This value is added here to align the result to our timescale
-- without messing around with the PLL.
......@@ -207,7 +207,7 @@ begin -- behavioral
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(acam_timebase_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied_d0(post_frac_multiplied_d0'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
......@@ -221,10 +221,10 @@ begin -- behavioral
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i(4 downto 0);
tag_dbg_raw_o(15 downto 11) <= acam_timebase_offset_i(4 downto 0);
tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
tag_dbg_raw_o(30 downto 24) <= raw_utc_i(6 downto 0);
tag_dbg_raw_o(31) <= acam_subcycle_offset_i(5);
tag_dbg_raw_o(31) <= acam_timebase_offset_i(5);
tag_valid_o <= '1';
else
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-02-12
-- Last update: 2013-07-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -168,7 +168,7 @@ architecture behavioral of fd_acam_timestamper is
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
raw_frac_i : in std_logic_vector(22 downto 0);
raw_start_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
acam_timebase_offset_i : in std_logic_vector(5 downto 0);
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
......@@ -225,7 +225,7 @@ architecture behavioral of fd_acam_timestamper is
signal start_count : unsigned(4 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal subcycle_offset : signed(5 downto 0);
signal timebase_offset : signed(5 downto 0);
signal gcr_input_en_d0 : std_logic;
......@@ -482,7 +482,7 @@ begin -- behave
if rst_n_i = '0' or regs_i.gcr_bypass_o = '1' then
start_count <= (others => '0');
subcycle_offset <= (others => '0');
timebase_offset <= (others => '0');
advance_coarse <= '0';
else
......@@ -492,7 +492,7 @@ begin -- behave
-- between the current start count and the LSBs of the new time value
-- and correct the timestamps later on.
if(csync_p1_i = '1') then
subcycle_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
timebase_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
end if;
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero
......@@ -856,7 +856,7 @@ begin -- behave
raw_coarse_i => std_logic_vector(raw_tag_coarse),
raw_frac_i => std_logic_vector(raw_tag_frac),
raw_start_offset_i => std_logic_vector(raw_tag_start_offset),
acam_subcycle_offset_i => std_logic_vector(subcycle_offset),
acam_timebase_offset_i => std_logic_vector(timebase_offset),
tag_valid_o => tag_valid_int,
tag_utc_o => tag_utc_o,
tag_coarse_o => tag_coarse,
......
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