port CHANGELOG to BE-CO-HT format

Described here: https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelinesSigned-off-by: Federico Vaga <federico.vaga@cern.ch>

port CHANGELOG to BE-CO-HT format
Described here: https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelinesSigned-off-by: Federico Vaga <federico.vaga@cern.ch>
ff801d80 · Federico Vaga · d1cde3be · ff801d80
Commit ff801d80 authored Jun 03, 2020 by Federico Vaga
Hide whitespace changes
Inline Side-by-side

Showing with 16 additions and 0 deletions

CHANGELOG.rst CHANGELOG.rst +16 -0

No files found.
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
-# Changelog
-All notable changes to this project will be documented in this file.
+..
+  SPDX-License-Identifier: CC-0.0
+  SPDX-FileCopyrightText: 2019 CERN

-The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
-and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+=========
+Changelog
+=========

-## [3.0.0] - 2020-06-02
-### Added
+3.0.0 - 2020-06-02
+==================
+
+Added
+-----
 - First release of Convention-based Fine Delay HW/GW/SW.
 - Added programmable delay line on the TDC start FPGA input to compensate for different delays on
-  TDC start signal from different production batches of the boards.
\ No newline at end of file
+  TDC start signal from different production batches of the boards.