Commits · 585895e26280b353ee92d5134573440b774f2223 · Projects / FMC DEL 1ns 4cha · Open Hardware Repository

02 Feb, 2015 1 commit
- circuit_board: synced with EDMS V6.1 release · 585895e2
  Tomasz Wlostowski authored Feb 02, 2015
  
  585895e2
09 Dec, 2014 3 commits
- top: updated to latest version of GN4124 core · a1af67a9
  Tomasz Wlostowski authored Dec 09, 2014
  
  a1af67a9
- hdl/ip_cores: updated submodules to latest versions (including WR Heisenbug fix) · e67d2ca1
  Tomasz Wlostowski authored Dec 09, 2014
  
  e67d2ca1
- doc/design-notes: minor fixes · c23f0572
  Tomasz Wlostowski authored Dec 09, 2014
  
  c23f0572
23 Sep, 2014 1 commit
- mechanical: heatsink design files · 7488357d
  Tomasz Wlostowski authored Sep 23, 2014
  
  7488357d
27 May, 2014 1 commit
- circuit_board: synced with EDMS V6.0 release · be77deff
  Tomasz Wlostowski authored May 27, 2014
  
  be77deff
26 Mar, 2014 1 commit
- hdl/top/spec: reduce fine '295 outputs drive strength on the SPEC too · 7dd0a8c3
  Tomasz Wlostowski authored Mar 26, 2014
  
  7dd0a8c3
25 Mar, 2014 3 commits
- hdl/syn/svec: migrate to ISE 14.5 · a3f676c4
  Tomasz Wlostowski authored Mar 25, 2014
  
  a3f676c4
- hdl/top/svec: reduce delay line control outputs drive stregths (fixes signal integrity issues) · cf1ce608
  Tomasz Wlostowski authored Mar 25, 2014
  
  cf1ce608
- hdl/rtl/fd_delay_line_arbiter.vhd: delay output by 1 cycle to improve timing closure · 6bf2c42b
  Tomasz Wlostowski authored Mar 25, 2014
  
  6bf2c42b
24 Mar, 2014 2 commits
- hdl/testbench/svec_wr_top: verify the new arbiter · 883c423a
  Tomasz Wlostowski authored Mar 24, 2014
  
  883c423a
- hdl/rtl/fd_delay_line_arbiter.vhd: rewritten for faster arbitration to never miss 600 ns deadline · 7dea47db
  Tomasz Wlostowski authored Mar 24, 2014
```
The commit also adds possibility of wiring the channel driver 0 and ACAM data valid strobes/state indication
to the front panel LEMO connectors on the SVEC carrier, for the purpose of debugging ACAM/output stage processing latency.
```
  7dea47db
19 Mar, 2014 5 commits
- hdl/[top,syn]: updated manifests and ISE projects to the latest submodule versions · c2353fcd
  Tomasz Wlostowski authored Mar 19, 2014
  
  c2353fcd
- hdl/[top,syn]: moved s[v|p]ec/wr to just svec/spec, there is no non-WhiteRabbit top level anymore · 68cd7428
  Tomasz Wlostowski authored Mar 19, 2014
  
  68cd7428
- hdl/top: default synthesis includes WR core firmware and exludes Etherbone · 6dd38ee3
  Tomasz Wlostowski authored Mar 19, 2014
  
  6dd38ee3
- hdl/top: removed redundant copies of spec_serial_dac(_arb), now they are in wr-cores · fad0bf61
  Tomasz Wlostowski authored Mar 19, 2014
  
  fad0bf61
- hdl/ip_cores: updated wr-cores to include the SOF fix · d5b92e69
  Tomasz Wlostowski authored Mar 19, 2014
  
  d5b92e69
18 Mar, 2014 5 commits
- hdl/ip_cores: updated wr-cores to contain ep_packet_filter timing fix · de2431fb
  Tomasz Wlostowski authored Mar 18, 2014
  
  de2431fb
- hdl/syn: bundled release 2.1 of the WR core for WRC firmware integration · ce0d0232
  Tomasz Wlostowski authored Mar 18, 2014
  
  ce0d0232
- hdl/top/svec/wr/svec_top.ucf: relax inter-clock domain timing · 41151ff3
  Tomasz Wlostowski authored Mar 18, 2014
  
  41151ff3
- hdl/top/svec/wr/bicolor_led_ctrl.vhd: eliminate latch · 39480871
  Tomasz Wlostowski authored Mar 18, 2014
  
  39480871
- hdl/ip_cores: add gn4124-core as a submodule · 556b339f
  Tomasz Wlostowski authored Mar 18, 2014
  
  556b339f
17 Mar, 2014 2 commits
- hdl/syn/svec: updated ISE project to use local ip_cores/ repo checkouts · 70c0e033
  Tomasz Wlostowski authored Mar 17, 2014
  
  70c0e033
- hdl/rtl/fd_spi_dac_arbiter.vhd: mask WR Core DAC write signal with TCR.WR_ENABLE bit · e93ae297
  Tomasz Wlostowski authored Mar 17, 2014
```
This prevents the WR Core from messing up with the FD DAC settings when an incorrect
WRC firmware is loaded.
```
  e93ae297
13 Mar, 2014 2 commits
- hdl: added submodule references for SVEC release bitstream · d3e6cf13
  Tomasz Wlostowski authored Mar 13, 2014
  
  d3e6cf13
- hdl/top/svec: removed redundant xvme64x_core.vhd · ff0bea1b
  Tomasz Wlostowski authored Mar 13, 2014
  
  ff0bea1b
21 Jan, 2014 3 commits
- hdl/top/svec: fixed WRPC SDB bridge offset (should be relative) · 8ea34c3d
  Tomasz Wlostowski authored Jan 21, 2014
  
  8ea34c3d
- hdl/top/svec: WR support for both mezzanines (migrated to WRPC with multiple aux clock support) · bd459526
  Tomasz Wlostowski authored Jan 21, 2014
  
  bd459526
- hdl/top/svec: moved vme64x-core repo to git · 881f5c68
  Tomasz Wlostowski authored Jan 21, 2014
  
  881f5c68
17 Jan, 2014 3 commits
- hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release.… · cec52178
  Tomasz Wlostowski authored Jan 17, 2014
```
hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release. Enabled synthesis with embedded firmware by default.
```
  cec52178
- hdl/top/spec: added missing constraints on GTP RX clock · c617457b
  Tomasz Wlostowski authored Jan 17, 2014
  
  c617457b
- hdl/top/spec: migrate to git version of the Gennum core · 27f3e721
  Tomasz Wlostowski authored Jan 17, 2014
  
  27f3e721
04 Dec, 2013 1 commit
- rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong… · d78c214c
  Tomasz Wlostowski authored Dec 04, 2013
```
rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong alignment handling bug in wbgen)
```
  d78c214c
07 Nov, 2013 1 commit
- doc: long term test report · b2a1db4e
  Tomasz Wlostowski authored Nov 07, 2013
  
  b2a1db4e
09 Sep, 2013 1 commit
- hdl/top/spec/wr/spec_top.vhd: updated to the multi-aux clock WR core · ddbf6ec0
  Tomasz Wlostowski authored Sep 09, 2013
  
  ddbf6ec0
25 Jul, 2013 1 commit
- rtl/fd_channel_wishbone_slave: FRR register should be in clk_ref domain · 605cafb3
  Tomasz Wlostowski authored Jul 25, 2013
  
  605cafb3
09 Jul, 2013 1 commit
- doc/design-notes: fixes after Erik's feedback · e8cf7876
  Tomasz Wlostowski authored Jul 09, 2013
  
  e8cf7876
04 Jul, 2013 3 commits
- doc/design-notes: fixes after Javier's feedback · dc61674f
  Tomasz Wlostowski authored Jul 04, 2013
  
  dc61674f
- hdl/rtl: fix unclear timebase offset signal name · f5f3da02
  Tomasz Wlostowski authored Jul 04, 2013
  
  f5f3da02
- rtl,doc: fixes in Wishbone registers documentation · 4e9db31d
  Tomasz Wlostowski authored Jul 04, 2013
  
  4e9db31d