FMC DEL 1ns 4cha issueshttps://ohwr.org/project/fmc-delay-1ns-8cha/issues2022-11-14T13:12:16Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/45Setup time violation on FPGA_TDC_START2022-11-14T13:12:16ZTomasz WlostowskiSetup time violation on FPGA_TDC_STARTPTS tests of a recent batch of Fine Delays show that some boards have a 'raw' (uncalibrated) in->out delay of 914 ns, while some others have 922 ns. There's a clear 8 ns jump here.
We've identified it's caused by setup time violation of the FPGA TDC start signal, which causes the FPGA's internal time base counter to be shifted by 8ns. A programmable IODELAY has been added to the firmware to mitigate this issue (branch tom-iodelay in git).
Things still to do (so that we don't forget):
- program the IODELAY in the device driver
- detect 922ns-calibrated boards in the driver and subtract the extra 8ns
- SPEC/SPEXI versions of the IODELAY-fixed VHDL
- release the bitstreams & drivers.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/1EEPROM type not compatible with VITA 57.12019-02-12T09:07:41ZDimitris LampridisEEPROM type not compatible with VITA 57.1In order to comply with VITA 57.1 standard, the FMC EEPROM needs to be
changed to 24C02.Federico VagaFederico Vagahttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/2Strange hang of an FD on SPEC in slot 11 (only) of KISS 4U2019-02-12T09:07:42ZErik van der BijStrange hang of an FD on SPEC in slot 11 (only) of KISS 4UReported at CERN under https://issues.cern.ch/browse/DRVR-178
In short, loading the FMC-FDELAY firmware/driver causes a Kontron
KISS-4U-762 to freeze right after load, with a certain probability, if
the SPEC is living in slot 11 (not in slot 10).
This is the phenomenon observed in DRVR-175. It has nothing to do with
the identity of the SPEC board or the fine delay; it happened with
different SPECs, FDs and crates, as long as the combination was
installed in slot 11.
We may conclude that the KISS 4U PCI-762 with spec+fine delay in slot 11
(4x) exhibits this behaviour. To be investigated (it might be a driver
bug, but looks more like a fine delay firmware problem related to some
PCI bus timing; no idea).
It does not seem the masterFIP exhibits this behaviour, but I have not
researched on the configurations used to test it (in particular,
avoidance of slot 11 seems unlikely, given that the 1x slots of the 4Us
are useless with the 4x PCIe connector of the SPEC).https://ohwr.org/project/fmc-delay-1ns-8cha/issues/3Strange hang of an FD on SVEC cards2019-02-12T09:07:42ZTomasz WlostowskiStrange hang of an FD on SVEC cardsOne of the FD mezzanines running on SVEC carrier we have at CERN (FD
S/N: 28, SVEC S/N: 101) has been reported by the user to stop delaying
pulses after running for a while. Observations:
\- The problem is reproducible (managed to crash the same
carrier+mezzanine in the lab after ~2 days of continuous work)
\- Never observed on other SVECs/FDs.
\- Entire FD\_CLK-driven part of the FD core appears to be down (no
clock?), hence no delay.
\- Reloading the drivers makes the card work again.
\- Possibility: power supply supervisor tripping (and resetting the
PLL)?
Investigate if it's a general problem or a damaged mezzanine.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/4AP1117 voltage regulator unstable2019-02-12T09:07:44ZTomasz WlostowskiAP1117 voltage regulator unstableThe AP1117 regulators (IC6, IC9 and IC21) used to produce clean supply
voltages for the ACAM TDC behave instably due to too low ESR of the
output decoupling capacitors. The voltages on VDDC\_OH, VDDQ\_TDC and
VDDC\_TDC may have as much as 400 mV of sawtooth-like ripple, which
causes TDC jitter outside the spec and test failure.
*Investigation:**
\- All cards from V5-2 batch (70 pieces) pass the tests. No oscillations
on LDOs were spotted. Datasheet for AP1117 from July 2012, used for
design of the V5-2 board says that the ESR of output capacitors should
be less than 0.5 ohm. Combined ESR of all decoupling capacitors is 0.075
- 0.15 ohm.
\- All cards from V6-0 pre-series fail the PTS due to LDO oscillations.
The newest datasheet, from June 2013 restricts the output capacitor ESR
range to 0.15 - 0.5 ohm. In this case, ESR of the decoupling capacitors
(C15, etc.) is too low.
\- Re-soldering IC9 from a V5-2 card to a V6-0 one fixed the issue (no
oscillations).
\- Does this mean AP1117's design was changed between the two revisions
of the datasheet?
*Solution:**
\- Leave only one 10 uF capacitor on each LDO's output.
\- Do not mount: C32, C59, C19, C14, C61, C66, C15.
*Notes:**
\- Despite the claims from ACAM's datasheet and PLL regulation circuit
design, recommending a huge decoupling capacitance, the modified V6-0
cards show even slightly better jitter performance than the V5-2 (1.07
bins rms vs 1.14 bins rms, 1 bin = 40.5 ps). Measurement was done for 2
V6-0 cards and 2 V5-2 cards.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/8V5 - lifetime of 16TQC10M capacitors lower than expected2022-11-14T16:45:44ZErik van der BijV5 - lifetime of 16TQC10M capacitors lower than expectedThe FMC DEL card runs quite hot when used in a PC on a SPEC carrier.
Temperatures around 65-85 degrees have been seen.
Early datasheets told that the 16TQC10M capacitors on the board would
have a lifetime of 63245 hours (2635 days) when used at 75 degrees.
However, the latest information received shows that it is only 16000
hours at 75 degrees. Four times as little\! There are 27 of those
capacitors on the
board.
Received the following info from Sanyo Panasonic regarding the life time of the 16TQC10M.
Life time of 16TQC10M is as below;
105℃ x 2,000
80℃=11,313 hours (1.3 yr)
75℃=16,000 hours (1.8 yr)
70℃=22,627 hours (2.6 yr)
65℃=32,000 hours (3.7 yr)
- We should have a look into this (understand better what is the
failure type, possibilities of replacing by other types).
See also the FAQ:
- [The FMC-DEL card runs quite
hot...](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/FAQ#q-the-fmc-del-card-runs-quite-hot-when-used-in-a-pc-on-a-spec-carrier-is-that-normal)
- [Did you take the high temperature into
account...](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/FAQ#q-did-you-take-the-high-temperature-into-account-when-designing-this-card)Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/10All versions: via capping under IC172022-11-29T15:48:57ZTomasz WlostowskiAll versions: via capping under IC17The vias under IC17 should be marked as filled/capped in the PCB
documentation for consistency with other QFN component thermal pads.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/13V5-0 - Add 10mm spacers,replace FMC front panel kit2022-12-14T13:13:45ZErik van der BijV5-0 - Add 10mm spacers,replace FMC front panel kitThe standoffs are not in the BOM file "arrangement-mat". They are
needed.
Replace the Xtech FMC front panel kit, the two spacers and the four
hexalobular screws by the following ELMA kit reference:
21M280-2
The ELMA 21M280-2 kit contains:
\- 1 FMC front panel
\- 1 O-ring
\- 2 10mm spacers
\- 8 M2.5x6mm screwsTomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/14V5-0 - P8V power supply startup problems2022-12-14T13:12:48ZTomasz WlostowskiV5-0 - P8V power supply startup problemsThe switched mode PSU (LT3503) on some cards (V5+) has problems with
starting up: it never exits current limit mode, because of high load
capacitance of the decoupling capacitors (10 x POSCAP 47 uF) combined
with their very low ESR.
As a result, we get very noisy P8V rail, which disturbs the ACAM delay
line PLL linear power supply, increasing the jitter of measured
timestamps 3-4 times. The bug was unnoticeable to the PTS because it
currently measures only average delay.
Actions:
1\. Replace all 47 uF POSCAPs with 10 uF POSCAPs (10 pcs / board)
2\. Update the PTS to characterize TDC jitter of each card.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/16V5-0 - Input clamping diode not clamping2022-12-12T09:19:48ZTomasz WlostowskiV5-0 - Input clamping diode not clampingThe I-V function of the Schottky diode D6 (HSMS-2802 - input clamping)
is not steep enough to clamp the input to +3.3V. For example, when
driving with 5 V pulses from a 50-ohm terminated source, the diode
current is approx 30 mA resulting in a dropout of ~1.5 V - so the diode
is not clamping the signal at all. On the other hand, Schottky diodes
with steeper I-V function have higher junction capacitance.
The previous version of the board used a BAR66 RF PIN diode, which did
clipping well but its' long recovery time (0.7 us) was causing spurious
TDC events (see issue 515). A workaround in VHDL was provided for that
purpose. Therefore, I recommend replacing D6 back with BAR66.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/17V4: Solder leaking2022-12-14T13:12:48ZTomasz WlostowskiV4: Solder leakingIn a recent batch of the V4-0 test series, we discovered that I2C and
IC7 thermal pads on the bottom layer were partially covered with solder
that leaked from nearby resistor pads. This happened because the holes
in the solder mask were enlarged during production, removing narrow
bridges that were separating the pads and preventing solder flow.
Verify with the DEM/manufacturer what solder mask expansion/sliver
values should be used to avoid such situations in the future and
possibly fix the PCB in a later release.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/18Input delay dependent on the source resistance and level2022-12-14T13:12:48ZTomasz WlostowskiInput delay dependent on the source resistance and levelR57 value (220R) was too high, causing integration of the input pulses
on the input capacitance. As a result, the input time offset was
dependent on the amplitude/resistance of the trigger source.
Fix: use smaller R57 value - tested with 22 ohms (large enough to limit
clamping diode current to 1A without significant integration).
To be included in EDA-02267-V4-1.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/19Input stage clipping diode causing deterioration of pulse edges2023-11-22T11:53:53ZTomasz WlostowskiInput stage clipping diode causing deterioration of pulse edgesThe BAR66 diode in the input stage was causing severe degradation of the
falling edge of the signal (with Tf \> 300 ns) when the input was
clamped due to too high amplitude of the pulses. This combined with
analog noise in the trigger resulted in spurious events in the TDC FIFO.
Fix: replace the diode with a fast Schottky RF diode. Tested with
HSMS-2802-TR1G.
To be included in EDA-02267-V4-1.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/20V4 - PCB specification missing information2023-10-27T10:03:19ZErik van der BijV4 - PCB specification missing informationThe PCB specification EDA-02267-V4\_specif has problems in the pdf
(missing info) and Excel (cell too small).
On page 2: cell with "Via holes are specified as to drilled hole size ;
for these holes the finished hole size is for reference only. Holes
receiving component leads or pins are specified as to finished hole
size; for these holes the drilled hole
size is for reference only. \*\*Holes Cap plating shall be in accordance
to IPC6012C - 3.6.2.11.2 Fig 3.16 and table"
- Correct info at
https://edms.cern.ch/nav/P:EDA-02267:V0/I:EDA-02267-V4-0:V0/TAB4Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/21V4 - BOM description switching regulator wrong2019-02-12T09:07:59ZErik van der BijV4 - BOM description switching regulator wrongThe board uses an LT1931AES5\#PBF for IC30. This is the 2.2 MHz version
of this IC (see
[datasheet](http://cds.linear.com/docs/Datasheet/1931fa.pdf)).
However, the description in the BOM reads "+16V to (-0.4V to -36V),
*1.2MHz* Inverting DC-DC Converters".
Actions
- Request DEM to correct the description
- Update the schematic with the new symbol
- Update production filesErik van der BijErik van der Bijhttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/22pulldown on TERM_ENABLE line2019-02-12T09:07:59ZTomasz Wlostowskipulldown on TERM_ENABLE lineAdd pulldown on TERM\_ENABLE, ensuring a known state of the termination
MOSFET when the card is reset.Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/24Add 3V regulator for the VM53S oscillator2023-10-27T10:03:19ZTomasz WlostowskiAdd 3V regulator for the VM53S oscillatorThe oscillator requires to be powered from 3V (not 3.3V). Add an
appropriate LDO (use SPEC as a reference design).Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/26V3 - Outer layer copper non-complient to IPC600A2019-02-12T09:08:02ZErik van der BijV3 - Outer layer copper non-complient to IPC600A- Outer layer copper thickness is 18um. This seems to be non-complient
to IPC600A.
- Impedance controlled layers wrongly marked. In the specification of
the PCB, 4 thicknesses are defined to be critical (with a '\*').
Check if these all are critical.
- Impedance controlled layers are nt symmetrical. Verify.
- Correct total thickness of board.
*See attached mail.**
### Files
* [EDA-02267-V3.txt](/uploads/e401886c276ca977920d12e6a23aaf5e/EDA-02267-V3.txt)Tomasz WlostowskiTomasz Wlostowskihttps://ohwr.org/project/fmc-delay-1ns-8cha/issues/29Wrong voltage/current rating of BSH103 transistors2019-02-12T09:08:05ZTomasz WlostowskiWrong voltage/current rating of BSH103 transistorsSchematics indicate max Vds of BSH103 is 50 V, while datasheet says it's
30 V. Update part description.https://ohwr.org/project/fmc-delay-1ns-8cha/issues/30[spec] Use PCI-e reset to reset the core and the card2019-02-12T09:08:06ZTomasz Wlostowski[spec] Use PCI-e reset to reset the core and the cardThe FD core keeps working after resetting the host PC.Tomasz WlostowskiTomasz Wlostowski